Displaying 2 results from an estimated 2 matches for "16xi1".
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16vi1
2016 Jun 29
0
Question about VectorLegalizer::ExpandStore() with v4i1
...ural model for
SIMD instruction sets, it seems to me.
As you say, the packed representation makes a lot of sense for AVX512.
But even the existing SSE and AVX instruction sets use a packed representation
in many cases. For example, the SSE operation movmskps produces a 4xi1
and pmovmskb produces 16xi1, both in packed form. In addition, any
icmp or fcmp operation can be easily implemented using two instructions
to produce packed i1 values. Our software relies on this packed
representation extensively.
>
> JinGu,
>
> Your analysis is correct, vectors of i1 are incorrectly legal...
2016 Jun 28
2
Question about VectorLegalizer::ExpandStore() with v4i1
On Tue, Jun 28, 2016 at 2:45 AM, jingu kang via llvm-dev
<llvm-dev at lists.llvm.org> wrote:
> Hi All,
>
> Can someone comment below question whether it is wrong or not please?
>
> 2016-06-25 7:52 GMT+01:00 jingu kang <jaykang10 at gmail.com>:
>> Hi All,
>>
>> I have a problem with VectorLegalizer::ExpandStore() with v4i1.
>>
>> Let's