Displaying 3 results from an estimated 3 matches for "16792fdd".
2011 Mar 26
0
[LLVMdev] Possible missed optimization?
On Mar 24, 2011, at 5:42 PM, Borja Ferrer wrote:
> The last copy instruction should be removed as pointed out above, but since R27R26 is killed in the load instruction it has to be emitted. About the insane amount of regclasses there, the load/store and the andi instructions take subsets of regs from the main register class, they cant work with all registers, that's why STW and LDW needs
2011 Mar 25
2
[LLVMdev] Possible missed optimization?
Hello, I've noticed the following issue while testing some codegen tests, i
would like to know if it's a missed optimization or i missed something out
here. This is for an out of tree backend im writing. I managed to reduce it
to the following C function:
void foo(int *a) // int here is 16bits
{
*a &= 0xFF;
}
This is the code before regalloc:
Live Ins: %R25R24
2011 Mar 26
2
[LLVMdev] Possible missed optimization?
...er class:
DREGSxDLDREGS=DLDREGS / DLDREGSxPTRREGS=PTRREGS, etc. That's why i think the
coalescer should work since the regclasses overlap completely.
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