search for: 160r

..." } Here's the tail-end of the log, with debugging turned on: $llc bugpoint.reduced.simplified.bc -debug ... 208B %vreg13:sub_64_1<def> = COPY %vreg34:sub_64_1; VecRegs:%vreg13,%vreg34 Considering merging to VecRegs with %vreg34 in %vreg13 RHS = %vreg34 [160r,240r:0)[240r,384B:1)[400B,480r:1)[480r,496r:2)[496r,672r:3) 0 at 160r 1 at 240r 2 at 480r 3 at 496r L00000020 [240r,384B:1)[400B,672r:1) 0 at x 1 at 240r L00000010 [160r,384B:1)[400B,672r:1) 0 at x 1 at 160r L00000002 [480r,480d:1)[496r,672r:0) 0 at 496r 1 at 480r L00000001 [480r,672r:0) 0 at...

...d from  16B%vreg17<def> = COPY %T1_W<kill>; R600_TReg32:%vreg17 register: %vreg17 +[16r,352r:0) 32B%vreg16<def> = COPY %T1_Z<kill>; R600_TReg32:%vreg16 register: %vreg16 +[32r,240r:0) 48B%vreg15<def> = COPY %T1_Y<kill>; R600_TReg32:%vreg15 register: %vreg15 +[48r,160r:0) 64B%vreg14<def> = COPY %T1_X<kill>; R600_TReg32:%vreg14 register: %vreg14 +[64r,96r:0) 80B%vreg18<def> = COPY %C1_X; R600_Reg32:%vreg18 register: %vreg18 +[80r,128r:0) 96B%vreg19:sel_x<def,read-undef> = COPY %vreg14<kill>; R600_Reg128:%vreg19 R600_TReg32:%vreg14 reg...

...> = COPY %T1_W<kill>; R600_TReg32:%vreg17 > register: %vreg17 +[16r,352r:0) > 32B%vreg16<def> = COPY %T1_Z<kill>; R600_TReg32:%vreg16 > register: %vreg16 +[32r,240r:0) > 48B%vreg15<def> = COPY %T1_Y<kill>; R600_TReg32:%vreg15 > register: %vreg15 +[48r,160r:0) > 64B%vreg14<def> = COPY %T1_X<kill>; R600_TReg32:%vreg14 > register: %vreg14 +[64r,96r:0) > 80B%vreg18<def> = COPY %C1_X; R600_Reg32:%vreg18 > register: %vreg18 +[80r,128r:0) > 96B%vreg19:sel_x<def,read-undef> = COPY %vreg14<kill>; > R600_Reg128:...

...if.else 112B %vreg2<def> = MOVri 0; GPRegs:%vreg2 register: %vreg2 +[112r,128r:0) 128B STWi13 <fi#0>, 0, %vreg2<kill>; mem:ST4[%retval] GPRegs:%vreg2 BB#3: # derived from return 160B %vreg4<def> = LDWi13 <fi#0>, 0; mem:LD4[%retval] GPRegs:%vreg4 register: %vreg4 +[160r,176r:0) 176B %R2<def> = COPY %vreg4<kill>; GPRegs:%vreg4 192B RET %R2<imp-use,kill> Computing live-in reg-units in ABI blocks. 0B BB#0 R2#0 Created 1 new intervals. ********** INTERVALS ********** R2 = [0B,16r:0)[176r,192r:1) 0 at 0B-phi 1 at 176r %vreg0 = [16r,32r:0) 0 at 16r %...

...0 /home/gnb/Maildir/new imap 10198 gnb 157r VDIR 255,7032 1093632 2917923 /home/gnb/Maildir/cur imap 10198 gnb 158r VDIR 255,7032 8192 5784160 /home/gnb/Maildir/new imap 10198 gnb 159r VDIR 255,7032 1093632 2917923 /home/gnb/Maildir/cur imap 10198 gnb 160r VDIR 255,7032 8192 5784160 /home/gnb/Maildir/new imap 10198 gnb 161r VDIR 255,7032 1093632 2917923 /home/gnb/Maildir/cur imap 10198 gnb 162r VDIR 255,7032 8192 5784160 /home/gnb/Maildir/new imap 10198 gnb 163r VDIR 255,7032 1093632 2917923 /home/...

...def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg5 register: %vreg5 +[96r,144r:0) 112B%vreg6<def> = ADD 0, 0, 1, 0, 0, 0, %vreg4<kill>, 0, 0, 0, %vreg5, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg6,%vreg4,%vreg5 register: %vreg6 +[112r,160r:0) 128B%vreg7<def> = MOV 1, 0, 0, 0, %vreg2, 1, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg7 R600_TReg32:%vreg2 register: %vreg7 +[128r,144r:0) 144B%vreg8<def> = ADD 0, 0, 1, 0, 0, 0, %vreg7<kill>, 0, 0, 0, %vreg5<kill>, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vr...

Hi Vincent, On 24/10/2012 23:26, Vincent Lejeune wrote: > Hi, > > I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below. > > The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is : > > // BEFORE LOOP >

Hi, I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below. The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is : // BEFORE LOOP ... Some COPYs.... 400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2