Displaying 18 results from an estimated 18 matches for "160b".
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2013 Mar 19
0
[LLVMdev] setCC and brcond
...CFG: BB#1(12) BB#2(20)
96B BB#1: derived from LLVM BB %if.then
Predecessors according to CFG: BB#0
112B %vreg3<def> = MOVri 1; GPRegs:%vreg3
128B STWi13 <fi#0>, 0, %vreg3<kill>; mem:ST4[%retval] GPRegs:%vreg3
144B BRrel <BB#3>
Successors according to CFG: BB#3
160B BB#2: derived from LLVM BB %if.else
Predecessors according to CFG: BB#0
176B %vreg2<def> = MOVri 0; GPRegs:%vreg2
192B STWi13 <fi#0>, 0, %vreg2<kill>; mem:ST4[%retval] GPRegs:%vreg2
Successors according to CFG: BB#3
208B BB#3: derived from LLVM BB %return
Predece...
2018 Sep 11
2
linear-scan RA
...> successors: %bb.3(0x80000000); %bb.3(100.00%)
>
> 80B %1:gr32 = MOV32ri 17
> 96B JMP_1 %bb.3
>
> 112B bb.2:
> ; predecessors: %bb.0
> successors: %bb.3(0x80000000); %bb.3(100.00%)
>
> 128B NOOP implicit %0:gr32
> 144B %1:gr32 = COPY %0:gr32
> 160B JMP_1 %bb.3
>
> 176B bb.3:
> ; predecessors: %bb.1, %bb.2
>
> 192B NOOP implicit %1:gr32
>
> # End machine code for function somefunc.
>
>
> If you look at the "intervals" (the class is a misnomer since nowadays it contains a list of ranges...) in t...
2017 Oct 13
2
Machine Scheduler on Power PC: Latency Limit and Register Pressure
...vreg0; mem:LD8[%num](tbaa=!4)
G8RC:%vreg2 G8RC_and_G8RC_NOX0:%vreg0
64B %vreg3<def> = LD 0, %vreg1; mem:LD8[%den](tbaa=!4)
G8RC:%vreg3 G8RC_and_G8RC_NOX0:%vreg1
144B %vreg7<def> = LD 8, %vreg0; mem:LD8[%arrayidx.1](tbaa=!4)
G8RC:%vreg7 G8RC_and_G8RC_NOX0:%vreg0
160B %vreg8<def> = LD 8, %vreg1; mem:LD8[%arrayidx2.1](tbaa=!4)
G8RC:%vreg8 G8RC_and_G8RC_NOX0:%vreg1
208B %vreg10<def> = LD 16, %vreg0;
mem:LD8[%arrayidx.2](tbaa=!4) G8RC:%vreg10 G8RC_and_G8RC_NOX0:%vreg0
224B %vreg11<def> = LD 16, %vreg1;
mem:LD8[%...
2018 Sep 11
2
linear-scan RA
...(100.00%)
> >
> > 80B %1:gr32 = MOV32ri 17
> > 96B JMP_1 %bb.3
> >
> > 112B bb.2:
> > ; predecessors: %bb.0
> > successors: %bb.3(0x80000000); %bb.3(100.00%)
> >
> > 128B NOOP implicit %0:gr32
> > 144B %1:gr32 = COPY %0:gr32
> > 160B JMP_1 %bb.3
> >
> > 176B bb.3:
> > ; predecessors: %bb.1, %bb.2
> >
> > 192B NOOP implicit %1:gr32
> >
> > # End machine code for function somefunc.
> >
> >
> > If you look at the "intervals" (the class is a misnomer since nowa...
2018 Sep 11
2
linear-scan RA
The phi instruction is irrelevant; just the way I think about things.
The question is if the allocator believes that t0 and t2 interfere.
Perhaps the coalescing example was too simple.
In the general case, we can't coalesce without a notion of interference.
My worry is that looking at interference by ranges of instruction numbers
leads to inaccuracies when a range is introduced by a copy.
2018 Sep 11
2
linear-scan RA
...MP_1 %bb.3
> >> >
> >> > 112B bb.2:
> >> > ; predecessors: %bb.0
> >> > successors: %bb.3(0x80000000); %bb.3(100.00%)
> >> >
> >> > 128B NOOP implicit %0:gr32
> >> > 144B %1:gr32 = COPY %0:gr32
> >> > 160B JMP_1 %bb.3
> >> >
> >> > 176B bb.3:
> >> > ; predecessors: %bb.1, %bb.2
> >> >
> >> > 192B NOOP implicit %1:gr32
> >> >
> >> > # End machine code for function somefunc.
> >> >
> >> >
>...
2020 Mar 31
2
[ARM] Register pressure with -mthumb forces register reload before each call
...4, $noreg, %3:tgpr, <regmask $lr $d8 $d9 $d10 $d11 $d12 $d13 $d14 $d15 $q4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 and 35 more...>, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit-def $sp
160B ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp
176B ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp
192B $r0 = COPY %0:tgpr
208B $r1 = COPY %1:tgpr
224B $r2 = COPY %2:tgpr
240B tBLXr 14, $noreg, %3:tgpr, <regmask $lr $d8 $d9 $d10 $d11 $d12...
2012 Oct 20
2
[LLVMdev] RegisterCoalescing pass crashes with ImplicitDef registers
...00_Reg32:%vreg6,%vreg4,%vreg5
128B%vreg7<def> = MOV 1, 0, 0, 0, %vreg2, 1, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg7 R600_TReg32:%vreg2
144B%vreg8<def> = ADD 0, 0, 1, 0, 0, 0, %vreg7<kill>, 0, 0, 0, %vreg5, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg8,%vreg7,%vreg5
160B%vreg10<def> = IMPLICIT_DEF; R600_Reg128:%vreg10
176B%vreg9<def,tied1> = INSERT_SUBREG %vreg10<tied0>, %vreg6<kill>, sel_x; R600_Reg128:%vreg9,%vreg10 R600_Reg32:%vreg6
192B%vreg11<def,tied1> = INSERT_SUBREG %vreg9<tied0>, %vreg8<kill>, sel_y; R600_Reg128:%v...
2020 Apr 07
2
[ARM] Register pressure with -mthumb forces register reload before each call
If I'm understanding what's going on in this test correctly, what's happening is:
* ARMTargetLowering::LowerCall prefers indirect calls when a function is called at least 3 times in minsize
* In thumb 1 (without -fno-omit-frame-pointer) we have effectively only 3 callee-saved registers (r4-r6)
* The function has three arguments, so those three plus the register we need to hold the
2020 Apr 15
4
[ARM] Register pressure with -mthumb forces register reload before each call
...4, $noreg, %3:tgpr, <regmask $lr $d8 $d9 $d10 $d11 $d12 $d13 $d14 $d15 $q4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 and 35 more...>, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit-def $sp
160B ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp
176B ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp
192B $r0 = COPY %0:tgpr
208B $r1 = COPY %2:tgpr
224B $r2 = COPY %1:tgpr
240B tBLXr 14, $noreg, %3:tgpr, <regmask $lr $d8 $d9 $d10 $d11 $d12...
2017 Oct 13
3
Machine Scheduler on Power PC: Latency Limit and Register Pressure
...a=!4) G8RC:%vreg2 G8RC_and_G8RC_NOX0:%vreg0
>> 64B %vreg3<def> = LD 0, %vreg1; mem:LD8[%den](tbaa=!4) G8RC:%vreg3 G8RC_and_G8RC_NOX0:%vreg1
>> 144B %vreg7<def> = LD 8, %vreg0; mem:LD8[%arrayidx.1](tbaa=!4) G8RC:%vreg7 G8RC_and_G8RC_NOX0:%vreg0
>> 160B %vreg8<def> = LD 8, %vreg1; mem:LD8[%arrayidx2.1](tbaa=!4) G8RC:%vreg8 G8RC_and_G8RC_NOX0:%vreg1
>> 208B %vreg10<def> = LD 16, %vreg0; mem:LD8[%arrayidx.2](tbaa=!4) G8RC:%vreg10 G8RC_and_G8RC_NOX0:%vreg0
>> 224B %vreg11<def> = LD 16, %v...
2018 Sep 11
2
linear-scan RA
...>>> 112B bb.2:
>>>>>> ; predecessors: %bb.0
>>>>>> successors: %bb.3(0x80000000); %bb.3(100.00%)
>>>>>>
>>>>>> 128B NOOP implicit %0:gr32
>>>>>> 144B %1:gr32 = COPY %0:gr32
>>>>>> 160B JMP_1 %bb.3
>>>>>>
>>>>>> 176B bb.3:
>>>>>> ; predecessors: %bb.1, %bb.2
>>>>>>
>>>>>> 192B NOOP implicit %1:gr32
>>>>>>
>>>>>> # End machine code for function somefunc...
2012 Oct 25
2
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...00_Reg32:%vreg2
register: %vreg2 +[112r,400r:0)
128B%vreg21:sel_x<def,read-undef> = COPY %vreg18<kill>; R600_Reg128:%vreg21 R600_Reg32:%vreg18
register: %vreg21 +[128r,176r:0)
144B%vreg23<def> = COPY %vreg19<kill>; R600_Reg128:%vreg23,%vreg19
register: %vreg23 +[144r,224r:0)
160B%vreg23:sel_y<def> = COPY %vreg15<kill>; R600_Reg128:%vreg23 R600_TReg32:%vreg15
register: %vreg23 replace range with [144r,160r:1) RESULT: [144r,160r:1)[160r,224r:0) 0 at 160r 1 at 144r
176B%vreg24<def> = COPY %vreg21<kill>; R600_Reg128:%vreg24,%vreg21
register: %vreg24 +[1...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...2 +[112r,400r:0)
> 128B%vreg21:sel_x<def,read-undef> = COPY %vreg18<kill>;
> R600_Reg128:%vreg21 R600_Reg32:%vreg18
> register: %vreg21 +[128r,176r:0)
> 144B%vreg23<def> = COPY %vreg19<kill>; R600_Reg128:%vreg23,%vreg19
> register: %vreg23 +[144r,224r:0)
> 160B%vreg23:sel_y<def> = COPY %vreg15<kill>; R600_Reg128:%vreg23
> R600_TReg32:%vreg15
> register: %vreg23 replace range with [144r,160r:1) RESULT:
> [144r,160r:1)[160r,224r:0) 0 at 160r 1 at 144r
> 176B%vreg24<def> = COPY %vreg21<kill>; R600_Reg128:%vreg24,%vreg21...
2012 Sep 18
2
[LLVMdev] liveness assertion problem in llc
...PredRegs:%vreg10 IntRegs:%vreg9 dbg:../src/getbits.c:46:1
96B JUMP <BB#2>, pred:%vreg10<kill>; PredRegs:%vreg10
Successors according to CFG: BB#2(12) BB#1(20)
112B BB#1:
Predecessors according to CFG: BB#0
128B %vreg27<def> = MOV32ri -1, pred:%noreg; IntRegs:%vreg27
160B JUMP <BB#5>, pred:%noreg
Successors according to CFG: BB#5
176B BB#2: derived from LLVM BB %while.cond.preheader
Predecessors according to CFG: BB#0
192B %vreg27<def> = MOV32ri 0, pred:%noreg; IntRegs:%vreg27
208B %vreg24<def> = CMPNEI %vreg6, 0, pred:%noreg; PredReg...
2020 Jun 26
2
How to implement load/store for vector predicate register
Hi,
I am planning to expanding the pseudo instructions in XXXTargetLowering::EmitInstrWithCustomInserter(), and use temporary virtual registers as operands.
If I use virtual registers, do I need to mark them as "early clobber"?
I saw that sometimes they marked virtual register as "early clobber" in EmitInstrWithCustomInserter() in MIPS backend.
What is the effect of marking a
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...= IMPLICIT_DEF; R600_Reg128:%vreg20
> 112B%vreg19<def,tied1> = INSERT_SUBREG %vreg20<tied0>, %vreg14, sel_x; R600_Reg128:%vreg19,%vreg20 R600_TReg32:%vreg14
> 128B%vreg2<def> = COPY %C1_Y; R600_Reg32:%vreg2
> 144B%vreg22<def> = IMPLICIT_DEF; R600_Reg128:%vreg22
> 160B%vreg21<def,tied1> = INSERT_SUBREG %vreg22<tied0>, %vreg18<kill>, sel_x; R600_Reg128:%vreg21,%vreg22 R600_Reg32:%vreg18
> 176B%vreg23<def,tied1> = INSERT_SUBREG %vreg19<tied0>, %vreg15, sel_y; R600_Reg128:%vreg23,%vreg19 R600_TReg32:%vreg15
> 192B%vreg24<def,ti...
2012 Oct 24
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...B%vreg20<def> = IMPLICIT_DEF; R600_Reg128:%vreg20
112B%vreg19<def,tied1> = INSERT_SUBREG %vreg20<tied0>, %vreg14, sel_x; R600_Reg128:%vreg19,%vreg20 R600_TReg32:%vreg14
128B%vreg2<def> = COPY %C1_Y; R600_Reg32:%vreg2
144B%vreg22<def> = IMPLICIT_DEF; R600_Reg128:%vreg22
160B%vreg21<def,tied1> = INSERT_SUBREG %vreg22<tied0>, %vreg18<kill>, sel_x; R600_Reg128:%vreg21,%vreg22 R600_Reg32:%vreg18
176B%vreg23<def,tied1> = INSERT_SUBREG %vreg19<tied0>, %vreg15, sel_y; R600_Reg128:%vreg23,%vreg19 R600_TReg32:%vreg15
192B%vreg24<def,tied1> =...