Displaying 5 results from an estimated 5 matches for "145850".
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135850
2020 Oct 29
0
[riscv] How do I use the RISC-V Vector extension instructions in LLVM IR?
...ere she and others were working on prototype support for the V extension. The work on support for the V extension has continued, but not via upstreaming the exact changes in that prototype - instead there is an RFC about code generation support: http://lists.llvm.org/pipermail/llvm-dev/2020-October/145850.html <http://lists.llvm.org/pipermail/llvm-dev/2020-October/145850.html> which includes links to proposed upstream patches implementing the RFC's approach.
I'm not sure the status of that RFC with respect to intrinsics for operations like vsetvl - but it seems likely to me that such...
2020 Sep 29
2
[riscv] How do I use the RISC-V Vector extension instructions in LLVM IR?
Hi Everyone,
I am wondering how to use RISC-V V (Vector) extension instructions in
LLVM IR. In 2019 Kruppe and Espasa gave a talk [1] overviewing the
Vector extension and on slide 16 [2] they show LLVM IR samples which use
the vector instructions through intrinsic functions, such as:
%vl = call i32 @llvm.riscv.vsetvl(i32 %n)
At the time of the talk (April 2019) LLVM support for the V
2009 Jan 13
0
Graphic Stutter in WoW
Good evening all,
I've got a pretty bad graphic stutter that happens every 2 seconds or so. Like the whole game is stopping graphically for a second then returning to normal for another 2 seconds.
I've seen the troubleshooting in the ubuntu forums here:
https://help.ubuntu.com/community/WorldofWarcraft/Troubleshooting#Glitch%20every%203-5%20sec.
I've added the SET gxApi
2019 Oct 31
20
[Bug 112185] New: Xorg hangs from time to time
https://bugs.freedesktop.org/show_bug.cgi?id=112185
Bug ID: 112185
Summary: Xorg hangs from time to time
Product: xorg
Version: unspecified
Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NEW
Severity: critical
Priority: not set
Component: Driver/nouveau
Assignee: nouveau at
2020 Nov 11
3
An update on scalable vectors in LLVM
...for scalable vectors today?
======================================
Today AArch64 SVE/SVE2 is probably the target with the most complete support, although
recently Roger Ferrer also shared a proposal on adding codegen for the RISCV V extension (http://lists.llvm.org/pipermail/llvm-dev/2020-October/145850.html).
* For AArch64 SVE/SVE2 we implemented support for the Arm’s C/C++ level intrinsics (https://developer.arm.com/documentation/100987/). This required changes to implement the calling convention, spilling and filling, adding a lot of the intrinsics to LLVM and Clang, and fixing up many code-...