Displaying 14 results from an estimated 14 matches for "144r".
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2020 Mar 31
2
[ARM] Register pressure with -mthumb forces register reload before each call
...ycrypt/blob/master/lib/source/ecc_dh.c#L139
Thanks,
Prathamesh
-------------- next part --------------
PreferIndirect: 1
PreferIndirect: 1
PreferIndirect: 1
Computing live-in reg-units in ABI blocks.
0B %bb.0 R0#0 R1#0 R2#0
Created 3 new intervals.
********** INTERVALS **********
R0 [0B,48r:0)[96r,144r:3)[192r,240r:2)[288r,336r:1) 0 at 0B-phi 1 at 288r 2 at 192r 3 at 96r
R1 [0B,32r:0)[112r,144r:3)[208r,240r:2)[304r,336r:1) 0 at 0B-phi 1 at 304r 2 at 208r 3 at 112r
R2 [0B,16r:0)[128r,144r:3)[224r,240r:2)[320r,336r:1) 0 at 0B-phi 1 at 320r 2 at 224r 3 at 128r
%0 [48r,288r:0) 0 at 48r weight:0.0...
2020 Apr 07
2
[ARM] Register pressure with -mthumb forces register reload before each call
If I'm understanding what's going on in this test correctly, what's happening is:
* ARMTargetLowering::LowerCall prefers indirect calls when a function is called at least 3 times in minsize
* In thumb 1 (without -fno-omit-frame-pointer) we have effectively only 3 callee-saved registers (r4-r6)
* The function has three arguments, so those three plus the register we need to hold the
2020 Apr 15
4
[ARM] Register pressure with -mthumb forces register reload before each call
...ine spilling tGPR:%9 [80r,152r:0) 0 at 80r weight:3.209746e-03
>From original %3
also spill snippet %8 [152r,232r:0) 0 at 152r weight:2.104167e-03
tBL 14, $noreg, &bar, implicit-def $lr, implicit $sp, implicit
killed $r0, implicit killed $r1, implicit killed $r2
folded: 144r tBL 14, $noreg, &"\E0\9C\06\A0\FC\7F",
implicit-def $lr, implicit $sp, implicit killed $r0, implicit killed
$r1, implicit killed $r2 :: (load 4 from constant-pool)
remat: 228r %10:tgpr = tLDRpci %const.0, 14, $noreg ::
(load 4 from constant-pool)
232e %...
2018 Sep 11
2
linear-scan RA
...> JMP_1 %bb.3
>
> bb.2:
> NOOP implicit %0
> %1 = COPY %0
> JMP_1 %bb.3
>
> bb.3:
> NOOP implicit %1
>
>
>
> $ llc -run-pass=liveintervals -debug-only=regalloc test.mir
> ********** INTERVALS **********
> %0 [16r,64B:0)[112B,144r:0) 0 at 16r weight:0.000000e+00
> %1 [80r,112B:1)[144r,176B:0)[176B,192r:2) 0 at 144r 1 at 80r 2 at 176B-phi weight:0.000000e+00
> RegMasks:
> ********** MACHINEINSTRS **********
> # Machine code for function somefunc: NoPHIs
>
> 0B bb.0:
> successors: %bb.2(0x80000000);...
2012 Oct 20
2
[LLVMdev] RegisterCoalescing pass crashes with ImplicitDef registers
...reg0 +[64r,416r:0)
80B%vreg4<def> = MOV 1, 0, 0, 0, %vreg3, 1, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg4 R600_TReg32:%vreg3
register: %vreg4 +[80r,112r:0)
96B%vreg5<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg5
register: %vreg5 +[96r,144r:0)
112B%vreg6<def> = ADD 0, 0, 1, 0, 0, 0, %vreg4<kill>, 0, 0, 0, %vreg5, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg6,%vreg4,%vreg5
register: %vreg6 +[112r,160r:0)
128B%vreg7<def> = MOV 1, 0, 0, 0, %vreg2, 1, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg7 R600_TReg32:%...
2018 Sep 11
2
linear-scan RA
...OOP implicit %0
> > %1 = COPY %0
> > JMP_1 %bb.3
> >
> > bb.3:
> > NOOP implicit %1
> >
> >
> >
> > $ llc -run-pass=liveintervals -debug-only=regalloc test.mir
> > ********** INTERVALS **********
> > %0 [16r,64B:0)[112B,144r:0) 0 at 16r weight:0.000000e+00
> > %1 [80r,112B:1)[144r,176B:0)[176B,192r:2) 0 at 144r 1 at 80r 2 at 176B-phi
> weight:0.000000e+00
> > RegMasks:
> > ********** MACHINEINSTRS **********
> > # Machine code for function somefunc: NoPHIs
> >
> > 0B bb.0:
>...
2018 Sep 11
2
linear-scan RA
The phi instruction is irrelevant; just the way I think about things.
The question is if the allocator believes that t0 and t2 interfere.
Perhaps the coalescing example was too simple.
In the general case, we can't coalesce without a notion of interference.
My worry is that looking at interference by ranges of instruction numbers
leads to inaccuracies when a range is introduced by a copy.
2018 Sep 11
2
linear-scan RA
...; >
> >> > bb.3:
> >> > NOOP implicit %1
> >> >
> >> >
> >> >
> >> > $ llc -run-pass=liveintervals -debug-only=regalloc test.mir
> >> > ********** INTERVALS **********
> >> > %0 [16r,64B:0)[112B,144r:0) 0 at 16r weight:0.000000e+00
> >> > %1 [80r,112B:1)[144r,176B:0)[176B,192r:2) 0 at 144r 1 at 80r 2 at 176B-phi
> weight:0.000000e+00
> >> > RegMasks:
> >> > ********** MACHINEINSTRS **********
> >> > # Machine code for function somefunc: NoPHI...
2012 Oct 25
2
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...> = COPY %T1_X<kill>; R600_TReg32:%vreg14
register: %vreg14 +[64r,96r:0)
80B%vreg18<def> = COPY %C1_X; R600_Reg32:%vreg18
register: %vreg18 +[80r,128r:0)
96B%vreg19:sel_x<def,read-undef> = COPY %vreg14<kill>; R600_Reg128:%vreg19 R600_TReg32:%vreg14
register: %vreg19 +[96r,144r:0)
112B%vreg2<def> = COPY %C1_Y; R600_Reg32:%vreg2
register: %vreg2 +[112r,400r:0)
128B%vreg21:sel_x<def,read-undef> = COPY %vreg18<kill>; R600_Reg128:%vreg21 R600_Reg32:%vreg18
register: %vreg21 +[128r,176r:0)
144B%vreg23<def> = COPY %vreg19<kill>; R600_Reg128:%vreg23...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...R600_TReg32:%vreg14
> register: %vreg14 +[64r,96r:0)
> 80B%vreg18<def> = COPY %C1_X; R600_Reg32:%vreg18
> register: %vreg18 +[80r,128r:0)
> 96B%vreg19:sel_x<def,read-undef> = COPY %vreg14<kill>;
> R600_Reg128:%vreg19 R600_TReg32:%vreg14
> register: %vreg19 +[96r,144r:0)
> 112B%vreg2<def> = COPY %C1_Y; R600_Reg32:%vreg2
> register: %vreg2 +[112r,400r:0)
> 128B%vreg21:sel_x<def,read-undef> = COPY %vreg18<kill>;
> R600_Reg128:%vreg21 R600_Reg32:%vreg18
> register: %vreg21 +[128r,176r:0)
> 144B%vreg23<def> = COPY %vreg19&l...
2018 Sep 11
2
linear-scan RA
...t;>>> NOOP implicit %1
>>>>>>
>>>>>>
>>>>>>
>>>>>> $ llc -run-pass=liveintervals -debug-only=regalloc test.mir
>>>>>> ********** INTERVALS **********
>>>>>> %0 [16r,64B:0)[112B,144r:0) 0 at 16r weight:0.000000e+00
>>>>>> %1 [80r,112B:1)[144r,176B:0)[176B,192r:2) 0 at 144r 1 at 80r 2 at 176B-phi weight:0.000000e+00
>>>>>> RegMasks:
>>>>>> ********** MACHINEINSTRS **********
>>>>>> # Machine code for funct...
2020 Apr 15
2
[ARM] Register pressure with -mthumb forces register reload before each call
...[80r,152r:0) 0 at 80r weight:3.209746e-03
> From original %3
> also spill snippet %8 [152r,232r:0) 0 at 152r weight:2.104167e-03
> tBL 14, $noreg, &bar, implicit-def $lr, implicit $sp, implicit
> killed $r0, implicit killed $r1, implicit killed $r2
> folded: 144r tBL 14, $noreg, &"\E0\9C\06\A0\FC\7F",
> implicit-def $lr, implicit $sp, implicit killed $r0, implicit killed
> $r1, implicit killed $r2 :: (load 4 from constant-pool)
> remat: 228r %10:tgpr = tLDRpci %const.0, 14, $noreg ::
> (load 4 from constant-pool)
>...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
Hi Vincent,
On 24/10/2012 23:26, Vincent Lejeune wrote:
> Hi,
>
> I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below.
>
> The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is :
>
> // BEFORE LOOP
>
2012 Oct 24
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
Hi,
I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below.
The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is :
// BEFORE LOOP
... Some COPYs....
400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2