Displaying 20 results from an estimated 20 matches for "144b".
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2016 Dec 22
1
Spill hoisting on RAL: looking for some debugging ideas
Hi,
I am debugging private backend and faced interesting problem:
sometimes spill hoisting creates double stores.
(some output from -debug-only=regalloc).
First hoisting:
Checking redundant spills for 0 at 16r in %vreg19
[16r,144B:0)[144B,240B:1)[240B,280r:2)[296r,416B:3)[416B,456r:4)[472r,592B:5)
0 at 16r 1 at 144B-phi 2 at 240B-phi
3 at 296r 4 at 416B-phi 5 at 472r
Merged to stack int: SS#0 [16r,592B:0) 0 at x
hoisted: 16r STbo %vreg19, <fi#0>
Second below:
Checking redundant spills for 0 at 16r in %vreg19
[16...
2018 Apr 23
2
pre-RA scheduling/live register analysis optimization (handle move) forcing spill of registers
...Class:%vreg6 FPUaOffsetClass:%vreg0,%vreg5
112B %vreg7<def> = COPY %vreg6; FPUaOffsetClass:%vreg7 FPUaROUTMULRegisterClass:%vreg6
128B %vreg8<def> = FADD_A_oo %vreg4, %vreg7, %RFLAGA<imp-def,dead>; FPUaROUTADDRegisterClass:%vreg8 FPUaOffsetClass:%vreg4,%vreg7
144B %FA_ROFF0<def> = COPY %vreg8; FPUaROUTADDRegisterClass:%vreg8
176B MOVSUTO_SU_os_rpc %SU_ROFF0<kill>, %RPC<imp-def,dead>
192B NOP
# End machine code for function addproddivConst.
handleMove 64B -> 104B: %vreg4<def> = COPY %vreg3; FPUaOff...
2020 Mar 31
2
[ARM] Register pressure with -mthumb forces register reload before each call
...%2:tgpr = COPY $r2
32B %1:tgpr = COPY $r1
48B %0:tgpr = COPY $r0
64B ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp
80B %3:tgpr = tLDRpci %const.0, 14, $noreg :: (load 4 from constant-pool)
96B $r0 = COPY %0:tgpr
112B $r1 = COPY %1:tgpr
128B $r2 = COPY %2:tgpr
144B tBLXr 14, $noreg, %3:tgpr, <regmask $lr $d8 $d9 $d10 $d11 $d12 $d13 $d14 $d15 $q4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 and 35 more...>, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implici...
2018 Sep 11
2
linear-scan RA
...JMP_1 %bb.2
>
> 64B bb.1:
> successors: %bb.3(0x80000000); %bb.3(100.00%)
>
> 80B %1:gr32 = MOV32ri 17
> 96B JMP_1 %bb.3
>
> 112B bb.2:
> ; predecessors: %bb.0
> successors: %bb.3(0x80000000); %bb.3(100.00%)
>
> 128B NOOP implicit %0:gr32
> 144B %1:gr32 = COPY %0:gr32
> 160B JMP_1 %bb.3
>
> 176B bb.3:
> ; predecessors: %bb.1, %bb.2
>
> 192B NOOP implicit %1:gr32
>
> # End machine code for function somefunc.
>
>
> If you look at the "intervals" (the class is a misnomer since nowadays it...
2017 Oct 13
2
Machine Scheduler on Power PC: Latency Limit and Register Pressure
...eg1
32B %vreg0<def> = COPY %X3; G8RC_and_G8RC_NOX0:%vreg0
48B %vreg2<def> = LD 0, %vreg0; mem:LD8[%num](tbaa=!4)
G8RC:%vreg2 G8RC_and_G8RC_NOX0:%vreg0
64B %vreg3<def> = LD 0, %vreg1; mem:LD8[%den](tbaa=!4)
G8RC:%vreg3 G8RC_and_G8RC_NOX0:%vreg1
144B %vreg7<def> = LD 8, %vreg0; mem:LD8[%arrayidx.1](tbaa=!4)
G8RC:%vreg7 G8RC_and_G8RC_NOX0:%vreg0
160B %vreg8<def> = LD 8, %vreg1; mem:LD8[%arrayidx2.1](tbaa=!4)
G8RC:%vreg8 G8RC_and_G8RC_NOX0:%vreg1
208B %vreg10<def> = LD 16, %vreg0;
mem:LD8[%arr...
2020 Apr 07
2
[ARM] Register pressure with -mthumb forces register reload before each call
If I'm understanding what's going on in this test correctly, what's happening is:
* ARMTargetLowering::LowerCall prefers indirect calls when a function is called at least 3 times in minsize
* In thumb 1 (without -fno-omit-frame-pointer) we have effectively only 3 callee-saved registers (r4-r6)
* The function has three arguments, so those three plus the register we need to hold the
2013 Mar 19
0
[LLVMdev] setCC and brcond
...Regs:%vreg1
80B BRrel <BB#1>
Successors according to CFG: BB#1(12) BB#2(20)
96B BB#1: derived from LLVM BB %if.then
Predecessors according to CFG: BB#0
112B %vreg3<def> = MOVri 1; GPRegs:%vreg3
128B STWi13 <fi#0>, 0, %vreg3<kill>; mem:ST4[%retval] GPRegs:%vreg3
144B BRrel <BB#3>
Successors according to CFG: BB#3
160B BB#2: derived from LLVM BB %if.else
Predecessors according to CFG: BB#0
176B %vreg2<def> = MOVri 0; GPRegs:%vreg2
192B STWi13 <fi#0>, 0, %vreg2<kill>; mem:ST4[%retval] GPRegs:%vreg2
Successors according t...
2020 Apr 15
4
[ARM] Register pressure with -mthumb forces register reload before each call
...%2:tgpr = COPY $r2
32B %1:tgpr = COPY $r1
48B %0:tgpr = COPY $r0
64B ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp
80B %3:tgpr = tLDRpci %const.0, 14, $noreg :: (load 4 from constant-pool)
96B $r0 = COPY %0:tgpr
112B $r1 = COPY %1:tgpr
128B $r2 = COPY %2:tgpr
144B tBLXr 14, $noreg, %3:tgpr, <regmask $lr $d8 $d9 $d10 $d11 $d12 $d13 $d14 $d15 $q4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 and 35 more...>, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implici...
2018 Sep 11
2
linear-scan RA
...; successors: %bb.3(0x80000000); %bb.3(100.00%)
> >
> > 80B %1:gr32 = MOV32ri 17
> > 96B JMP_1 %bb.3
> >
> > 112B bb.2:
> > ; predecessors: %bb.0
> > successors: %bb.3(0x80000000); %bb.3(100.00%)
> >
> > 128B NOOP implicit %0:gr32
> > 144B %1:gr32 = COPY %0:gr32
> > 160B JMP_1 %bb.3
> >
> > 176B bb.3:
> > ; predecessors: %bb.1, %bb.2
> >
> > 192B NOOP implicit %1:gr32
> >
> > # End machine code for function somefunc.
> >
> >
> > If you look at the "intervals&qu...
2018 Sep 11
2
linear-scan RA
The phi instruction is irrelevant; just the way I think about things.
The question is if the allocator believes that t0 and t2 interfere.
Perhaps the coalescing example was too simple.
In the general case, we can't coalesce without a notion of interference.
My worry is that looking at interference by ranges of instruction numbers
leads to inaccuracies when a range is introduced by a copy.
2012 Oct 20
2
[LLVMdev] RegisterCoalescing pass crashes with ImplicitDef registers
...SEL_OFF, 0; R600_Reg32:%vreg5
112B%vreg6<def> = ADD 0, 0, 1, 0, 0, 0, %vreg4<kill>, 0, 0, 0, %vreg5, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg6,%vreg4,%vreg5
128B%vreg7<def> = MOV 1, 0, 0, 0, %vreg2, 1, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg7 R600_TReg32:%vreg2
144B%vreg8<def> = ADD 0, 0, 1, 0, 0, 0, %vreg7<kill>, 0, 0, 0, %vreg5, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg8,%vreg7,%vreg5
160B%vreg10<def> = IMPLICIT_DEF; R600_Reg128:%vreg10
176B%vreg9<def,tied1> = INSERT_SUBREG %vreg10<tied0>, %vreg6<kill>, sel_x; R6...
2018 Sep 11
2
linear-scan RA
...%1:gr32 = MOV32ri 17
> >> > 96B JMP_1 %bb.3
> >> >
> >> > 112B bb.2:
> >> > ; predecessors: %bb.0
> >> > successors: %bb.3(0x80000000); %bb.3(100.00%)
> >> >
> >> > 128B NOOP implicit %0:gr32
> >> > 144B %1:gr32 = COPY %0:gr32
> >> > 160B JMP_1 %bb.3
> >> >
> >> > 176B bb.3:
> >> > ; predecessors: %bb.1, %bb.2
> >> >
> >> > 192B NOOP implicit %1:gr32
> >> >
> >> > # End machine code for function somef...
2003 Jan 14
2
2.4.21-pre3 - problems with ext3
...net_recvmsg_R__ver_inet_recvmsg+4e/70>
Trace; c0159fce <notify_change+2ce/350>
Trace; c013e2e6 <fd_install+b6/b70>
Trace; c0148bb3 <cdput+8c3/bb0>
Trace; c013f98d <generic_file_open+55d/650>
Trace; c013e397 <fd_install+167/b70>
Trace; c010770f <__read_lock_failed+144b/183c>
Code; f88ab5df <[jbd]journal_start+5f/c0>
00000000 <_EIP>:
Code; f88ab5df <[jbd]journal_start+5f/c0> <=====
0: 0f 0b ud2a <=====
Code; f88ab5e1 <[jbd]journal_start+61/c0>
2: f9 stc
Code; f88a...
2017 Oct 13
3
Machine Scheduler on Power PC: Latency Limit and Register Pressure
...0<def> = COPY %X3; G8RC_and_G8RC_NOX0:%vreg0
>> 48B %vreg2<def> = LD 0, %vreg0; mem:LD8[%num](tbaa=!4) G8RC:%vreg2 G8RC_and_G8RC_NOX0:%vreg0
>> 64B %vreg3<def> = LD 0, %vreg1; mem:LD8[%den](tbaa=!4) G8RC:%vreg3 G8RC_and_G8RC_NOX0:%vreg1
>> 144B %vreg7<def> = LD 8, %vreg0; mem:LD8[%arrayidx.1](tbaa=!4) G8RC:%vreg7 G8RC_and_G8RC_NOX0:%vreg0
>> 160B %vreg8<def> = LD 8, %vreg1; mem:LD8[%arrayidx2.1](tbaa=!4) G8RC:%vreg8 G8RC_and_G8RC_NOX0:%vreg1
>> 208B %vreg10<def> = LD 16, %vreg...
2018 Sep 11
2
linear-scan RA
...6B JMP_1 %bb.3
>>>>>>
>>>>>> 112B bb.2:
>>>>>> ; predecessors: %bb.0
>>>>>> successors: %bb.3(0x80000000); %bb.3(100.00%)
>>>>>>
>>>>>> 128B NOOP implicit %0:gr32
>>>>>> 144B %1:gr32 = COPY %0:gr32
>>>>>> 160B JMP_1 %bb.3
>>>>>>
>>>>>> 176B bb.3:
>>>>>> ; predecessors: %bb.1, %bb.2
>>>>>>
>>>>>> 192B NOOP implicit %1:gr32
>>>>>>
>>>...
2012 Oct 25
2
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...; R600_Reg128:%vreg19 R600_TReg32:%vreg14
register: %vreg19 +[96r,144r:0)
112B%vreg2<def> = COPY %C1_Y; R600_Reg32:%vreg2
register: %vreg2 +[112r,400r:0)
128B%vreg21:sel_x<def,read-undef> = COPY %vreg18<kill>; R600_Reg128:%vreg21 R600_Reg32:%vreg18
register: %vreg21 +[128r,176r:0)
144B%vreg23<def> = COPY %vreg19<kill>; R600_Reg128:%vreg23,%vreg19
register: %vreg23 +[144r,224r:0)
160B%vreg23:sel_y<def> = COPY %vreg15<kill>; R600_Reg128:%vreg23 R600_TReg32:%vreg15
register: %vreg23 replace range with [144r,160r:1) RESULT: [144r,160r:1)[160r,224r:0) 0 at 160...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...reg14
> register: %vreg19 +[96r,144r:0)
> 112B%vreg2<def> = COPY %C1_Y; R600_Reg32:%vreg2
> register: %vreg2 +[112r,400r:0)
> 128B%vreg21:sel_x<def,read-undef> = COPY %vreg18<kill>;
> R600_Reg128:%vreg21 R600_Reg32:%vreg18
> register: %vreg21 +[128r,176r:0)
> 144B%vreg23<def> = COPY %vreg19<kill>; R600_Reg128:%vreg23,%vreg19
> register: %vreg23 +[144r,224r:0)
> 160B%vreg23:sel_y<def> = COPY %vreg15<kill>; R600_Reg128:%vreg23
> R600_TReg32:%vreg15
> register: %vreg23 replace range with [144r,160r:1) RESULT:
> [144r,160...
2020 Jun 26
2
How to implement load/store for vector predicate register
Hi,
I am planning to expanding the pseudo instructions in XXXTargetLowering::EmitInstrWithCustomInserter(), and use temporary virtual registers as operands.
If I use virtual registers, do I need to mark them as "early clobber"?
I saw that sometimes they marked virtual register as "early clobber" in EmitInstrWithCustomInserter() in MIPS backend.
What is the effect of marking a
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...gt; = COPY %C1_X; R600_Reg32:%vreg18
> 96B%vreg20<def> = IMPLICIT_DEF; R600_Reg128:%vreg20
> 112B%vreg19<def,tied1> = INSERT_SUBREG %vreg20<tied0>, %vreg14, sel_x; R600_Reg128:%vreg19,%vreg20 R600_TReg32:%vreg14
> 128B%vreg2<def> = COPY %C1_Y; R600_Reg32:%vreg2
> 144B%vreg22<def> = IMPLICIT_DEF; R600_Reg128:%vreg22
> 160B%vreg21<def,tied1> = INSERT_SUBREG %vreg22<tied0>, %vreg18<kill>, sel_x; R600_Reg128:%vreg21,%vreg22 R600_Reg32:%vreg18
> 176B%vreg23<def,tied1> = INSERT_SUBREG %vreg19<tied0>, %vreg15, sel_y; R600_Reg12...
2012 Oct 24
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...4
80B%vreg18<def> = COPY %C1_X; R600_Reg32:%vreg18
96B%vreg20<def> = IMPLICIT_DEF; R600_Reg128:%vreg20
112B%vreg19<def,tied1> = INSERT_SUBREG %vreg20<tied0>, %vreg14, sel_x; R600_Reg128:%vreg19,%vreg20 R600_TReg32:%vreg14
128B%vreg2<def> = COPY %C1_Y; R600_Reg32:%vreg2
144B%vreg22<def> = IMPLICIT_DEF; R600_Reg128:%vreg22
160B%vreg21<def,tied1> = INSERT_SUBREG %vreg22<tied0>, %vreg18<kill>, sel_x; R600_Reg128:%vreg21,%vreg22 R600_Reg32:%vreg18
176B%vreg23<def,tied1> = INSERT_SUBREG %vreg19<tied0>, %vreg15, sel_y; R600_Reg128:%vreg23,...