Displaying 1 result from an estimated 1 matches for "13520fb5".
2014 Jul 13
2
[LLVMdev] IMUL x86 instruction
Hi,
The x86 CPU IMUL instruction has forms such as:
IMUL reg
EDX:EAX ← EAX ∗ reg
reg, EAX and EDX are 32bit registers.
How can I represent this sort of instruction in LLVM IR ?
It is really a 32bit * 32 bit = 64 bit, but no LLVM IR exists to do that.
Or, a similar question:
What LLVM IR would produce this IMUL instruction form?
For context, I am writing a x86 to LLVM IR decompiler, so wish to