search for: 128bits

...ey are stored using an APInt object. APInt (lib/Support/APInt.cpp) uses an array of uint64_t if more than two are needed or an inline uint64_t in the APInt object. So, yes, they are heap allocated. This is for compile time constants. At run time, the back ends don't support anything over 128bits (currently), except lli in interpreter mode. The interpreter uses APInt instances to compute all integer operations (including very large numbers). Reid >Sandro >_______________________________________________ >LLVM Developers mailing list >LLVMdev at cs.uiuc.edu http://llvm...

Where does the storage for large bit width integers come from? Are very large numbers heap allocated? Sandro

...:AES128+EDH Before I made this change clients were connecting with the following cipher in the log file: ECDHE-ECDSA-AES256-SHA (256/256 bits) After the change the log now says: ECDHE-ECDSA-AES128-GCM-SHA256 (128/128 bits) Is this an improvement (or more secure) despite going from 256bits to 128bits? Thanks!

...sing an APInt object. APInt (lib/Support/APInt.cpp) uses an > array of uint64_t if more than two are needed or an inline uint64_t in > the APInt object. So, yes, they are heap allocated. This is for > compile time constants. At run time, the back ends don't support > anything over 128bits (currently), except lli in interpreter mode. The > interpreter uses APInt instances to compute all integer operations > (including very large numbers). > > Reid > > >Sandro > >_______________________________________________ > >LLVM Developers mailing list > >L...

...align 16 !11 = !DILocalVariable(name: "x", scope: !4, file: !1, line: 2, type: !12) !12 = !DIBasicType(name: "long double", size: 128, align: 128, encoding: DW_ATE_float) !13 = !DIExpression() which happens because llvm knows that fp80s are 80bits, while clang declares them as 128bits in the debug info. We might have to special case this in the verifier, but before we do that, I wanted to ask about the following: Reading the DWARF standard, it seems like the following would be a valid description of an X86 80bit long double: DW_TAG_base_type DW_AT_name "long double"...

...t;> cipher in the log file: >> >> ECDHE-ECDSA-AES256-SHA (256/256 bits) >> >> After the change the log now says: >> >> ECDHE-ECDSA-AES128-GCM-SHA256 (128/128 bits) >> >> Is this an improvement (or more secure) despite going from 256bits to >> 128bits? > > yes it is because AES-GCM is currently the best cipher suite while there > is no point for AES256, if AES128 will fall then it likely affects > AES256 too and according to Brcue Schneier years ago AES128 has even > less problems then AES256 (too lazy for google it again) >...

...ead? I have many instructions that work irrespective of the data type. By allowing multiple types to work in a single register class, this reduces the number of times I have to duplicate code. For, example, I have a 128bit copy that works on i32, i64, f32, f64 data along with vector types up to 128bits in length. Tablegen should be smart enough to figure out that if my 128 bit register class has the 32bit and 64 bit register classes as subclasses, then a pattern written for the 128bit register class should also work for the sub types. This is standard object oriented programming. Throw all the co...

...0.0: GTT: 512M 0x60000000 - 0x7FFFFFFF [ 46.236000] [drm] Generation 2 PCI interface, using max accessible memory [ 46.316000] radeon 0000:80:00.0: VRAM: 128M 0xFFFFFFFFC0000000 - 0xFFFFFFFFC7FFFFFF (128M used) [ 46.420000] [drm] Detected VRAM RAM=128M, BAR=128M [ 46.476000] [drm] RAM width 128bits DDR [ 46.524000] [TTM] Zone kernel: Available graphics memory: 3077188 kiB [ 46.604000] [TTM] Zone dma32: Available graphics memory: 2097152 kiB [ 46.680000] [TTM] Initializing pool allocator [ 46.732000] [drm] radeon: 128M of VRAM memory ready [ 46.792000] [drm] radeon: 512M of GTT me...

...t; [ 46.236000] [drm] Generation 2 PCI interface, using max accessible memory >> [ 46.316000] radeon 0000:80:00.0: VRAM: 128M 0xFFFFFFFFC0000000 - >> 0xFFFFFFFFC7FFFFFF (128M used) >> [ 46.420000] [drm] Detected VRAM RAM=128M, BAR=128M >> [ 46.476000] [drm] RAM width 128bits DDR >> [ 46.524000] [TTM] Zone kernel: Available graphics memory: 3077188 kiB >> [ 46.604000] [TTM] Zone dma32: Available graphics memory: 2097152 kiB >> [ 46.680000] [TTM] Initializing pool allocator >> [ 46.732000] [drm] radeon: 128M of VRAM memory ready >&gt...

...t. - Arbitrary bit-size integers: I really like having these in the IR. I dislike fretting at the high-level about exactly what size an integer is, thus I've directly exposed LLVM's ability to have arbitrary bit sizes. (I just need a large-integer division routine now to fully support > 128bits.) - Exception handling: The landing pads and the ExceptionDemo got me a lot of the way to implementing exception handling. - Clang: Having a C and C++ compiler which can emit IR has been extremely helpful in deconstructing features of those languages. Slowly I'm working my way through every...

...ts were connecting with the following > cipher in the log file: > > ECDHE-ECDSA-AES256-SHA (256/256 bits) > > After the change the log now says: > > ECDHE-ECDSA-AES128-GCM-SHA256 (128/128 bits) > > Is this an improvement (or more secure) despite going from 256bits to > 128bits? yes it is because AES-GCM is currently the best cipher suite while there is no point for AES256, if AES128 will fall then it likely affects AES256 too and according to Brcue Schneier years ago AES128 has even less problems then AES256 (too lazy for google it again) -------------- next part --...

...ject. APInt (lib/Support/APInt.cpp) uses an >> array of uint64_t if more than two are needed or an inline uint64_t in >> the APInt object. So, yes, they are heap allocated. This is for >> compile time constants. At run time, the back ends don't support >> anything over 128bits (currently), except lli in interpreter mode. The >> interpreter uses APInt instances to compute all integer operations >> (including very large numbers). >> >> Reid >> >>> Sandro >>> _______________________________________________ >>> LLVM De...

...- 0x7FFFFFFF > [ 46.236000] [drm] Generation 2 PCI interface, using max accessible memory > [ 46.316000] radeon 0000:80:00.0: VRAM: 128M 0xFFFFFFFFC0000000 - > 0xFFFFFFFFC7FFFFFF (128M used) > [ 46.420000] [drm] Detected VRAM RAM=128M, BAR=128M > [ 46.476000] [drm] RAM width 128bits DDR > [ 46.524000] [TTM] Zone kernel: Available graphics memory: 3077188 kiB > [ 46.604000] [TTM] Zone dma32: Available graphics memory: 2097152 kiB > [ 46.680000] [TTM] Initializing pool allocator > [ 46.732000] [drm] radeon: 128M of VRAM memory ready > [ 46.792000] [dr...

Hi All First the essentials: dovecot --version: 2.2.15 /usr/local/etc/dovecot/conf.d/10-ssl.conf: ssl = required ssl_cert = </usr/local/openssl/certs/mail.domain.com.chained.dovecot.ecdsa.crt ssl_key = </usr/local/openssl/certs/mail.domain.com.ecdsa.key ssl_protocols = !SSLv2 !SSLv3 ssl_cipher_list =

...] [drm] Generation 2 PCI interface, using max accessible memory >>> [ 46.316000] radeon 0000:80:00.0: VRAM: 128M 0xFFFFFFFFC0000000 - >>> 0xFFFFFFFFC7FFFFFF (128M used) >>> [ 46.420000] [drm] Detected VRAM RAM=128M, BAR=128M >>> [ 46.476000] [drm] RAM width 128bits DDR >>> [ 46.524000] [TTM] Zone kernel: Available graphics memory: 3077188 kiB >>> [ 46.604000] [TTM] Zone dma32: Available graphics memory: 2097152 kiB >>> [ 46.680000] [TTM] Initializing pool allocator >>> [ 46.732000] [drm] radeon: 128M of VRAM memo...

...ufflevar} `VECTOR_SHUFFLE_VAR(VEC1, VEC2, VEC3)` See [*shufflevector*](#shufflevector). # AArch64 Specific Changes ## Instruction Selection In order to allow proper instruction selection there must be a direct mapping from MVTs to SVE registers. SVE data registers have a length in multiples of 128bits (with 128bits being the minimum) and predicate registers have a bit for every byte of a data register. Given the 128bit minimum we map scalable vector MVTs whose static component is also 128bits (e.g. MVT::nxv4i32) directly to SVE data registers. Scalable vector MVTs with an `i1` element type and...

Hi all, Does anyone have any experience porting libvorbis to platforms with small total memory sizes? Specifically, I'm trying to figure out if it's feasible to run Ogg Vorbis decoding on one of the PlayStation 3's SPU's -- secondary processors with only 256kb of local memory. It looks like out of the box the memory footprint of libvorbis is roughly: ~130k code ~60k static

On Oct 22, 2008, at 1:28 PM, Villmow, Micah wrote: > Is there a simple way to specify the relationship between two > different register classes of various sizes and alignments as being > legal to convert between them? I don't get it. What does it mean to "convert" between two register classes? You can move between different register classes. > I have my backend

Is there a simple way to specify the relationship between two different register classes of various sizes and alignments as being legal to convert between them? I have my backend written up using a single register class for i32, i64, f32 and f64 types, however, because the type information is not propagated down to the machine instruction register level, it is not known to me how to determine

...other MMX/SSE subset being utilised) than if vscale=16. If fixed-width/short vectors are more beneficial for some algorithm, I'd recommend using fixed-width vectors directly. It would be up to the target to lower that to the vector instruction set. For AArch64, this can be done using Neon (max 128bits) or with SVE/SVE2 using a 'fixed-width' predicate mask, e.g. vl4 for a predicate of 4 elements, even when the vector capacity is larger than 4. > would it be reasonable to assume that predication *always* is to be > used in combination with vscale? or is it the intention to > [ev...