Displaying 20 results from an estimated 33 matches for "112b".
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1127
2018 Apr 23
2
pre-RA scheduling/live register analysis optimization (handle move) forcing spill of registers
...tB), (COPY_TO_REGCLASS (FDIV_A_oo FPUaOffsetOperand:$OffsetA,FPUaOffsetOperand:$OffsetB),FPUaOffsetClass)>;
The instruction lowering goes as expected all instances of FMUL_A_oo are followed by a COPY, freeing the usage of FPUaROUTMULRegisterClass.
These COPY are at positions 64B and 112B in the example below. So far, so good.
My problem arise in some pre-RA instruction scheduling optimization moving these COPY at later positions 104B and 112B.
The new code sequence leaves two FMUL_A_oo without COPY. So this requires 2 registers from FPUaROUTMULRegisterClass (which only includes FA...
2013 Aug 02
0
[LLVMdev] Missing optimization - constant parameter
...aa=!"any pointer") GR64:%vreg1,%vreg0
64B %vreg2<def> = MOV64ri 12345123400; GR64:%vreg2
80B MOV64mr %vreg0, 1, %noreg, 0, %noreg, %vreg2;
mem:ST8[@val](tbaa=!"long long") GR64:%vreg0,%vreg2
96B %RDI<def> = COPY %vreg2; GR64:%vreg2
112B TCRETURNdi64 <ga:@xtr>, 0, <regmask>, %RSP<imp-use>,
%RDI<imp-use,kill>
into
0B BB#0: derived from LLVM BB %entry
16B %vreg0<def> = MOV64rm %RIP, 1, %noreg,
<ga:@val>[TF=5], %noreg; mem:LD8[GOT] GR64:%vreg0
32B %vreg1<...
2012 Jun 08
0
[LLVMdev] Strong vs. default phi elimination and single-reg classes
On Jun 7, 2012, at 7:31 PM, Hal Finkel wrote:
> 112B BB#1: derived from LLVM BB %for.body, ADDRESS TAKEN
> Predecessors according to CFG: BB#0 BB#1
> %vreg12<def> = PHI %vreg13, <BB#1>, %vreg11, <BB#0>;CTRRC8:%vreg12,%vreg13,%vreg11
> %vreg13<def> = COPY %vreg12<kill>; CTRRC8:%vreg13,%vreg12
> %...
2018 Sep 11
2
linear-scan RA
...ri 17
> JMP_1 %bb.3
>
> bb.2:
> NOOP implicit %0
> %1 = COPY %0
> JMP_1 %bb.3
>
> bb.3:
> NOOP implicit %1
>
>
>
> $ llc -run-pass=liveintervals -debug-only=regalloc test.mir
> ********** INTERVALS **********
> %0 [16r,64B:0)[112B,144r:0) 0 at 16r weight:0.000000e+00
> %1 [80r,112B:1)[144r,176B:0)[176B,192r:2) 0 at 144r 1 at 80r 2 at 176B-phi weight:0.000000e+00
> RegMasks:
> ********** MACHINEINSTRS **********
> # Machine code for function somefunc: NoPHIs
>
> 0B bb.0:
> successors: %bb.2(0x800000...
2013 Aug 02
2
[LLVMdev] Missing optimization - constant parameter
For the little C test program where a constant is stored in memory and
also
used as a parameter:
#include <stdint.h>
uint64_t val, *p;
extern uint64_t xtr( uint64_t);
uint64_t caller() {
uint64_t x;
p = &val;
x = 12345123400L;
*p = x;
return xtr(x);
}
clang (3.2, 3.3 and svn) generates the following X86 code (at -O3):
caller:
movq
2012 Jun 08
2
[LLVMdev] Strong vs. default phi elimination and single-reg classes
...t;, %vreg2; GPRC:%vreg3 G8RC:%vreg2
%vreg9<def> = COPY %vreg4<kill>; GPRC:%vreg9,%vreg4
%vreg10<def> = RLDICL %vreg9<kill>, 0, 32; GPRC:%vreg10,%vreg9
%vreg11<def> = MTCTR8r %vreg10<kill>; CTRRC8:%vreg11 GPRC:%vreg10
Successors according to CFG: BB#1
112B BB#1: derived from LLVM BB %for.body, ADDRESS TAKEN
Predecessors according to CFG: BB#0 BB#1
%vreg12<def> = PHI %vreg13, <BB#1>, %vreg11,
<BB#0>;CTRRC8:%vreg12,%vreg13,%vreg11
%vreg5<def> = LDtoc <ga:@a>, %X2; G8RC:%vreg5
%vreg6<def> = LWZ 0, %vreg...
2013 Aug 02
2
[LLVMdev] Missing optimization - constant parameter
...t;) GR64:%vreg1,%vreg0
> 64B %vreg2<def> = MOV64ri 12345123400; GR64:%vreg2
> 80B MOV64mr %vreg0, 1, %noreg, 0, %noreg, %vreg2;
> mem:ST8[@val](tbaa=!"long long") GR64:%vreg0,%vreg2
> 96B %RDI<def> = COPY %vreg2; GR64:%vreg2
> 112B TCRETURNdi64 <ga:@xtr>, 0, <regmask>, %RSP<imp-use>,
> %RDI<imp-use,kill>
>
> into
>
> 0B BB#0: derived from LLVM BB %entry
> 16B %vreg0<def> = MOV64rm %RIP, 1, %noreg,
> <ga:@val>[TF=5], %noreg; mem:LD8[GOT] GR6...
2018 Sep 11
2
linear-scan RA
...NOOP implicit %0
> > %1 = COPY %0
> > JMP_1 %bb.3
> >
> > bb.3:
> > NOOP implicit %1
> >
> >
> >
> > $ llc -run-pass=liveintervals -debug-only=regalloc test.mir
> > ********** INTERVALS **********
> > %0 [16r,64B:0)[112B,144r:0) 0 at 16r weight:0.000000e+00
> > %1 [80r,112B:1)[144r,176B:0)[176B,192r:2) 0 at 144r 1 at 80r 2 at 176B-phi
> weight:0.000000e+00
> > RegMasks:
> > ********** MACHINEINSTRS **********
> > # Machine code for function somefunc: NoPHIs
> >
> > 0B bb.0:...
2018 Sep 11
2
linear-scan RA
The phi instruction is irrelevant; just the way I think about things.
The question is if the allocator believes that t0 and t2 interfere.
Perhaps the coalescing example was too simple.
In the general case, we can't coalesce without a notion of interference.
My worry is that looking at interference by ranges of instruction numbers
leads to inaccuracies when a range is introduced by a copy.
2018 Sep 11
2
linear-scan RA
...t;> >
> >> > bb.3:
> >> > NOOP implicit %1
> >> >
> >> >
> >> >
> >> > $ llc -run-pass=liveintervals -debug-only=regalloc test.mir
> >> > ********** INTERVALS **********
> >> > %0 [16r,64B:0)[112B,144r:0) 0 at 16r weight:0.000000e+00
> >> > %1 [80r,112B:1)[144r,176B:0)[176B,192r:2) 0 at 144r 1 at 80r 2 at 176B-phi
> weight:0.000000e+00
> >> > RegMasks:
> >> > ********** MACHINEINSTRS **********
> >> > # Machine code for function somefunc:...
2013 Aug 05
0
[LLVMdev] Missing optimization - constant parameter
...t; > 64B %vreg2<def> = MOV64ri 12345123400; GR64:%vreg2
> > 80B MOV64mr %vreg0, 1, %noreg, 0, %noreg, %vreg2;
> > mem:ST8[@val](tbaa=!"long long") GR64:%vreg0,%vreg2
> > 96B %RDI<def> = COPY %vreg2; GR64:%vreg2
> > 112B TCRETURNdi64 <ga:@xtr>, 0, <regmask>, %RSP<imp-use>,
> > %RDI<imp-use,kill>
> >
> > into
> >
> > 0B BB#0: derived from LLVM BB %entry
> > 16B %vreg0<def> = MOV64rm %RIP, 1, %noreg,
> > <ga:@val>...
2012 Jun 12
2
[LLVMdev] Assert in live update from MI scheduler.
...essors according to CFG: BB#1
48B BB#1: derived from LLVM BB %for.cond
Predecessors according to CFG: BB#0 BB#1
80B %vreg1<def> = COPY %vreg10<kill>; IntRegs:%vreg1,%vreg10
96B %vreg10<def> = LDriw %vreg9<kill>, 0; mem:LD4[%stack.0.in]
IntRegs:%vreg10,%vreg9
112B %vreg9<def> = ADD_ri %vreg10, 8; IntRegs:%vreg9,%vreg10
128B %vreg6<def> = CMPEQri %vreg10, 0; PredRegs:%vreg6 IntRegs:%vreg10
176B JMP_cNot %vreg6<kill>, <BB#1>, %PC<imp-def>; PredRegs:%vreg6
192B JMP <BB#2>
Successors according to CFG: BB#2...
2018 Sep 11
2
linear-scan RA
...gt;>>>> NOOP implicit %1
>>>>>>
>>>>>>
>>>>>>
>>>>>> $ llc -run-pass=liveintervals -debug-only=regalloc test.mir
>>>>>> ********** INTERVALS **********
>>>>>> %0 [16r,64B:0)[112B,144r:0) 0 at 16r weight:0.000000e+00
>>>>>> %1 [80r,112B:1)[144r,176B:0)[176B,192r:2) 0 at 144r 1 at 80r 2 at 176B-phi weight:0.000000e+00
>>>>>> RegMasks:
>>>>>> ********** MACHINEINSTRS **********
>>>>>> # Machine code for...
2012 Jun 08
2
[LLVMdev] Strong vs. default phi elimination and single-reg classes
On Thu, 7 Jun 2012 22:14:00 -0700
Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote:
>
> On Jun 7, 2012, at 7:31 PM, Hal Finkel wrote:
>
> > 112B BB#1: derived from LLVM BB %for.body, ADDRESS TAKEN
> > Predecessors according to CFG: BB#0 BB#1
> > %vreg12<def> = PHI %vreg13, <BB#1>, %vreg11,
> > <BB#0>;CTRRC8:%vreg12,%vreg13,%vreg11 %vreg13<def> = COPY
> > %vreg12<kill>; CTRR...
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
...> 48B BB#1: derived from LLVM BB %for.cond
> Predecessors according to CFG: BB#0 BB#1
> 80B %vreg1<def> = COPY %vreg10<kill>; IntRegs:%vreg1,%vreg10
> 96B %vreg10<def> = LDriw %vreg9<kill>, 0; mem:LD4[%stack.0.in]
> IntRegs:%vreg10,%vreg9
> 112B %vreg9<def> = ADD_ri %vreg10, 8; IntRegs:%vreg9,%vreg10
> 128B %vreg6<def> = CMPEQri %vreg10, 0; PredRegs:%vreg6 IntRegs:%vreg10
> 176B JMP_cNot %vreg6<kill>, <BB#1>, %PC<imp-def>; PredRegs:%vreg6
> 192B JMP <BB#2>
> Successors acco...
2013 Mar 19
0
[LLVMdev] setCC and brcond
...reg0
48B %vreg1<def> = CMPri %vreg0, 0; CondRegs:%vreg1 GPRegs:%vreg0
64B BRcondrel %vreg1<kill>, <BB#2>; CondRegs:%vreg1
80B BRrel <BB#1>
Successors according to CFG: BB#1(12) BB#2(20)
96B BB#1: derived from LLVM BB %if.then
Predecessors according to CFG: BB#0
112B %vreg3<def> = MOVri 1; GPRegs:%vreg3
128B STWi13 <fi#0>, 0, %vreg3<kill>; mem:ST4[%retval] GPRegs:%vreg3
144B BRrel <BB#3>
Successors according to CFG: BB#3
160B BB#2: derived from LLVM BB %if.else
Predecessors according to CFG: BB#0
176B %vreg2<def> = M...
2020 Mar 31
2
[ARM] Register pressure with -mthumb forces register reload before each call
...n %2
0B bb.0.entry:
liveins: $r0, $r1, $r2
16B %2:tgpr = COPY $r2
32B %1:tgpr = COPY $r1
48B %0:tgpr = COPY $r0
64B ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp
80B %3:tgpr = tLDRpci %const.0, 14, $noreg :: (load 4 from constant-pool)
96B $r0 = COPY %0:tgpr
112B $r1 = COPY %1:tgpr
128B $r2 = COPY %2:tgpr
144B tBLXr 14, $noreg, %3:tgpr, <regmask $lr $d8 $d9 $d10 $d11 $d12 $d13 $d14 $d15 $q4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 and 35 more...>, implicit-def dead $lr, implicit $s...
2012 Oct 20
2
[LLVMdev] RegisterCoalescing pass crashes with ImplicitDef registers
...R600_TReg32:%vreg1
64B%vreg0<def> = COPY %T1_W; R600_TReg32:%vreg0
80B%vreg4<def> = MOV 1, 0, 0, 0, %vreg3, 1, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg4 R600_TReg32:%vreg3
96B%vreg5<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg5
112B%vreg6<def> = ADD 0, 0, 1, 0, 0, 0, %vreg4<kill>, 0, 0, 0, %vreg5, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg6,%vreg4,%vreg5
128B%vreg7<def> = MOV 1, 0, 0, 0, %vreg2, 1, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg7 R600_TReg32:%vreg2
144B%vreg8<def> = ADD 0, 0,...
2012 Jun 11
0
[LLVMdev] scoreboard hazard det. and instruction groupings
On Jun 11, 2012, at 12:07 PM, Hal Finkel <hfinkel at anl.gov> wrote:
> Looking at VLIWPacketizerList::PacketizeMIs, it seems like the
> instructions are first scheduled (via some external scheme?), and then
> packetized 'in order'. Is that correct?
Anshu?
> In the PowerPC grouping scheme, resources are assigned on a group
> basis (by the instruction dispatching
2020 Apr 07
2
[ARM] Register pressure with -mthumb forces register reload before each call
If I'm understanding what's going on in this test correctly, what's happening is:
* ARMTargetLowering::LowerCall prefers indirect calls when a function is called at least 3 times in minsize
* In thumb 1 (without -fno-omit-frame-pointer) we have effectively only 3 callee-saved registers (r4-r6)
* The function has three arguments, so those three plus the register we need to hold the