Displaying 3 results from an estimated 3 matches for "1117d32d".
2007 Apr 23
1
[LLVMdev] Instruction pattern type inference problem
...'isInt' includes all the
integer vector types, causing tablegen to not be able to infer all
the types in the pattern.
--
Christopher Lamb
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2007 Apr 23
0
[LLVMdev] Instruction pattern type inference problem
On Sun, 22 Apr 2007, Christopher Lamb wrote:
> I have a back end which has both scalar and vector registers that
> alias each other. I'm having a problem generating the ISel from
> tablegen that appears only when a vector register class is declared
> to contain integer vectors. At that moment tablegen doesn't seem to
> be able to infer integer types in patterns that it was
2007 Apr 23
4
[LLVMdev] Instruction pattern type inference problem
I have a back end which has both scalar and vector registers that
alias each other. I'm having a problem generating the ISel from
tablegen that appears only when a vector register class is declared
to contain integer vectors. At that moment tablegen doesn't seem to
be able to infer integer types in patterns that it was able to
before, but I'm not clear on why that's the