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2013 Jan 23
4
[LLVMdev] Instruction Constraints Question
We've discovered a problem in the AVX2 gather patterns X86InstrSSE.td.
According to the AVX2 manual, no two of the destination register, vector
index register and mask register can be the same. The patterns in
X86InstrSSE.td are missing this constraint and it's possible to generate
an illegal instruction.
It doesn't look like TableGen supports Constraints beyond EARLY_CLOBBER
and