search for: 1072r

...1)[1040r,1120r:0)  0 at 1040r 1 at 1024r 1056B%vreg9<def> = COPY %vreg6:sel_z<kill>; R600_Reg32:%vreg9 R600_Reg128:%vreg6 register: %vreg9 +[1056r,1104r:0) 1072B%vreg38<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 1; R600_Reg32:%vreg38 register: %vreg38 +[1072r,1088r:0) 1088B%vreg11<def> = ADD_INT 0, 0, 1, 0, 0, 0, %vreg7<kill>, 0, 0, 0, %vreg38<kill>, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg11,%vreg7,%vreg38 register: %vreg11 +[1088r,1136r:0) 1104B%vreg47<def> = COPY %vreg9<kill>; R600_Reg32:%vreg47,%vreg9 registe...

...at 1024r > 1056B%vreg9<def> = COPY %vreg6:sel_z<kill>; R600_Reg32:%vreg9 > R600_Reg128:%vreg6 > register: %vreg9 +[1056r,1104r:0) > 1072B%vreg38<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, > pred:%PRED_SEL_OFF, 1; R600_Reg32:%vreg38 > register: %vreg38 +[1072r,1088r:0) > 1088B%vreg11<def> = ADD_INT 0, 0, 1, 0, 0, 0, %vreg7<kill>, 0, 0, 0, > %vreg38<kill>, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; > R600_Reg32:%vreg11,%vreg7,%vreg38 > register: %vreg11 +[1088r,1136r:0) > 1104B%vreg47<def> = COPY %vreg9<kill>; R600_R...

Hi Vincent, On 24/10/2012 23:26, Vincent Lejeune wrote: > Hi, > > I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below. > > The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is : > > // BEFORE LOOP >

Hi, I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below. The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is : // BEFORE LOOP ... Some COPYs.... 400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2