Displaying 4 results from an estimated 4 matches for "1072b".
Did you mean:
1072
2012 Oct 25
2
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...reg37<kill>; R600_Reg128:%vreg10 R600_Reg32:%vreg37
register: %vreg10 replace range with [1024r,1040r:1) RESULT: [1024r,1040r:1)[1040r,1120r:0) 0 at 1040r 1 at 1024r
1056B%vreg9<def> = COPY %vreg6:sel_z<kill>; R600_Reg32:%vreg9 R600_Reg128:%vreg6
register: %vreg9 +[1056r,1104r:0)
1072B%vreg38<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 1; R600_Reg32:%vreg38
register: %vreg38 +[1072r,1088r:0)
1088B%vreg11<def> = ADD_INT 0, 0, 1, 0, 0, 0, %vreg7<kill>, 0, 0, 0, %vreg38<kill>, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg11,%v...
2012 Oct 24
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...32:%vreg37 R600_Reg128:%vreg6
1024B%vreg10<def> = COPY %vreg36<kill>; R600_Reg128:%vreg10,%vreg36
1040B%vreg10:sel_w<def> = COPY %vreg37<kill>; R600_Reg128:%vreg10 R600_Reg32:%vreg37
1056B%vreg9<def> = COPY %vreg6:sel_z<kill>; R600_Reg32:%vreg9 R600_Reg128:%vreg6
1072B%vreg38<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 1; R600_Reg32:%vreg38
1088B%vreg11<def> = ADD_INT 0, 0, 1, 0, 0, 0, %vreg7<kill>, 0, 0, 0, %vreg38<kill>, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg11,%vreg7,%vreg38
1104B%vreg47<def>...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...28:%vreg6
> 1024B%vreg10<def> = COPY %vreg36<kill>; R600_Reg128:%vreg10,%vreg36
> 1040B%vreg10:sel_w<def> = COPY %vreg37<kill>; R600_Reg128:%vreg10 R600_Reg32:%vreg37
> 1056B%vreg9<def> = COPY %vreg6:sel_z<kill>; R600_Reg32:%vreg9 R600_Reg128:%vreg6
> 1072B%vreg38<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 1; R600_Reg32:%vreg38
> 1088B%vreg11<def> = ADD_INT 0, 0, 1, 0, 0, 0, %vreg7<kill>, 0, 0, 0, %vreg38<kill>, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg11,%vreg7,%vreg38
> 1104B%vreg47...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...> R600_Reg32:%vreg37
> register: %vreg10 replace range with [1024r,1040r:1) RESULT:
> [1024r,1040r:1)[1040r,1120r:0) 0 at 1040r 1 at 1024r
> 1056B%vreg9<def> = COPY %vreg6:sel_z<kill>; R600_Reg32:%vreg9
> R600_Reg128:%vreg6
> register: %vreg9 +[1056r,1104r:0)
> 1072B%vreg38<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1,
> pred:%PRED_SEL_OFF, 1; R600_Reg32:%vreg38
> register: %vreg38 +[1072r,1088r:0)
> 1088B%vreg11<def> = ADD_INT 0, 0, 1, 0, 0, 0, %vreg7<kill>, 0, 0, 0,
> %vreg38<kill>, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0;...