Displaying 1 result from an estimated 1 matches for "1030182".
2013 May 02
8
[LLVMdev] Handling Masked Vector Operations
We're looking at how to handle masked vector operations in architectures
like Knight's Corner. In our case, we have to translate from a fully
vectorized IR that has mask support to llvm IR which does not have mask
support.
For non-trapping instructions this is fairly straightforward:
; Input
t1 = add t2, t3, mask
; llvm IR -- assuming we want zeros in the false positions, which is not