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10260,7
2012 Oct 30
2
[LLVMdev] how to define extending vector load patterns?
I have an operation which loads a 16 bit block of data as 2 8-bit
elements, sign extends the both parts to 32 bits and stores the result
into 64-bit vector register.
How can I define the pattern for this?
just using [(set V2I32Regs:$result, (sextloadv2i8 ADDRrr:$address))]
gives me error that extloav2i8 is not defined.
(the same principle works for scalar sextload)
So I need to define it