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1022537
2012 May 22
2
[LLVMdev] Match operands
I'm trying to implement the standalone assembler for mips and I have encountered a problem in instruction operands matcher.
In mips instruction set there are math instructions with two format flags in the mnemonic, one for source and one for destination register.
For example ceil.w.s means both source and destination are F32 registers while ceil.l.d means both source and destination are F64