Displaying 8 results from an estimated 8 matches for "100c1c".
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2014 Oct 21
3
Questions about some PFB registers on NVAC cards
...1 of register 100c14 fixes
the issue on that card. Other NVAC cards are working great without that trick,
and it seems they have that bit enabled by default. What is the role of that
bit, and when should it be turned on?
Before enabling 100c14's bit 1, the Nvidia driver writes some value into 100c1c.
Leaving the default value, or writing some random value seemed to have no
effect. What is this register used for?
Thanks in advance for your help!
Best regards,
Pierre Moreau
[1]: https://bugs.freedesktop.org/show_bug.cgi?id=27501
2014 Dec 01
1
Questions about some PFB registers on NVAC cards
...0x00000000
> > NV_PFB_NISO_POLLER_CFG_FLUSH_ENABLE_ENABLED
> > 0x00000001
Out of curiosity, what do DNISO and HOSTNB mean?
> >
> > > Before enabling 100c14's bit 1, the Nvidia driver writes some
> > > value
> > > into 100c1c.
> > > Leaving the default value, or writing some random value seemed to
> > > have no
> > > effect. What is this register used for?
> >
> > 100c1c is one of three registers which control the (upper bits of
> > the
> > 32-byte
> > aligned) me...
2014 Nov 26
0
Questions about some PFB registers on NVAC cards
...SH_ENABLE 16:16
NV_PFB_NISO_POLLER_CFG_FLUSH_ENABLE_DISABLED 0x00000000
NV_PFB_NISO_POLLER_CFG_FLUSH_ENABLE_ENABLED 0x00000001
> Before enabling 100c14's bit 1, the Nvidia driver writes some value into 100c1c.
> Leaving the default value, or writing some random value seemed to have no
> effect. What is this register used for?
100c1c is one of three registers which control the (upper bits of the 32-byte
aligned) memory locations that the pollers use:
#define NV_PFB_NISO_POLLER_DNISO_BASE_ADR...
2014 Oct 03
1
[PATCH v2 1/2] drm/nouveau/fb/nv50: Add PFB writes
...50: Add PFB writes")
This fix a GPU lockup on 9400M (NVAC) when using acceleration, see
https://bugs.freedesktop.org/show_bug.cgi?id=27501
v2:
- Move code to subdev/fb/nv50.c as suggested by Roy Spliet;
- Remove arbitrary writes to 100c18/100c24 as suggested by Roy Spliet;
- Replace write to 100c1c of arbitrary value by the address of a scratch page
as proposed by Ilia Mirkin;
- Remove enabling of bits 16 and 0 as they don't yield in any changes.
Signed-off-by: Pierre Moreau <pierre.morrow at free.fr>
---
drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c | 11 +++++++++++
1 file cha...
2014 Oct 21
0
Questions about some PFB registers on NVAC cards
...1 of register 100c14 fixes
the issue on that card. Other NVAC cards are working great without that trick,
and it seems they have that bit enabled by default. What is the role of that
bit, and when should it be turned on?
Before enabling 100c14's bit 1, the Nvidia driver writes some value into 100c1c.
Leaving the default value, or writing some random value seemed to have no
effect. What is this register used for?
Thanks in advance for your help!
Best regards,
Pierre Moreau
[1]: https://bugs.freedesktop.org/show_bug.cgi?id=27501
2014 Dec 10
2
[PATCH RESEND 1/2] Allow noaccel to be a pci address
Signed-off-by: Pierre Moreau <pierre.morrow at free.fr>
---
drm/nouveau_drm.c | 16 +++++++++++-----
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/drm/nouveau_drm.c b/drm/nouveau_drm.c
index afb93bb..ffa1e4f 100644
--- a/drm/nouveau_drm.c
+++ b/drm/nouveau_drm.c
@@ -61,9 +61,10 @@ MODULE_PARM_DESC(debug, "debug string to pass to driver core");
static char
2014 Dec 10
0
[PATCH v3 2/2] fb/nvaa: Enable non-isometric poller on NVAA/NVAC
...atch "drm/nouveau/fb/nv50: Add PFB writes")
This fix a GPU lockup on 9400M (NVAC) when using acceleration, see
https://bugs.freedesktop.org/show_bug.cgi?id=27501
v2:
- Move code to subdev/fb/nv50.c as suggested by Roy Spliet;
- Remove arbitrary writes to 100c18/100c24
- Replace write to 100c1c of arbitrary value by the address of a scratch page
as proposed by Ilia Mirkin;
- Remove enabling of bits 16 and 0 as they don't yield in any changes.
v3:
- Move code to subdev/fb/nvaa.c as suggested by Ilia Mirkin.
The following changes were made thanks to information provided by Robert Mor...
2014 Dec 11
1
[PATCH v3 2/2] fb/nvaa: Enable non-isometric poller on NVAA/NVAC
...B writes")
>
> This fix a GPU lockup on 9400M (NVAC) when using acceleration, see
> https://bugs.freedesktop.org/show_bug.cgi?id=27501
>
> v2:
> - Move code to subdev/fb/nv50.c as suggested by Roy Spliet;
> - Remove arbitrary writes to 100c18/100c24
> - Replace write to 100c1c of arbitrary value by the address of a scratch page
> as proposed by Ilia Mirkin;
> - Remove enabling of bits 16 and 0 as they don't yield in any changes.
>
> v3:
> - Move code to subdev/fb/nvaa.c as suggested by Ilia Mirkin.
> The following changes were made thanks to infor...