Displaying 5 results from an estimated 5 matches for "100c14".
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2014 Oct 21
3
Questions about some PFB registers on NVAC cards
...an 9400M (NVAC) card,
a PFIFO interrupt 0x00400000 is thrown during the initialisation of that card
(sometime after PFIFO and PGRAPH initialisation) and the laptop will lockup [1],
forcing users to load Nouveau without acceleration.
After some investigation, I found that enabling bit 1 of register 100c14 fixes
the issue on that card. Other NVAC cards are working great without that trick,
and it seems they have that bit enabled by default. What is the role of that
bit, and when should it be turned on?
Before enabling 100c14's bit 1, the Nvidia driver writes some value into 100c1c.
Leaving the d...
2014 Dec 01
1
Questions about some PFB registers on NVAC cards
...> Hi Robert,
>
> Thanks a lot for your response!
>
> ----- Mail original -----
> > On Wed, Oct 22, 2014 at 12:55:23AM +0200, pierre.morrow at free.fr
> > wrote:
> > [...]
> > > After some investigation, I found that enabling bit 1 of register
> > > 100c14 fixes
> > > the issue on that card. Other NVAC cards are working great
> > > without
> > > that trick,
> > > and it seems they have that bit enabled by default. What is the
> > > role of that
> > > bit, and when should it be turned on?
> >...
2014 Nov 26
0
Questions about some PFB registers on NVAC cards
On Wed, Oct 22, 2014 at 12:55:23AM +0200, pierre.morrow at free.fr wrote:
[...]
> After some investigation, I found that enabling bit 1 of register 100c14 fixes
> the issue on that card. Other NVAC cards are working great without that trick,
> and it seems they have that bit enabled by default. What is the role of that
> bit, and when should it be turned on?
Register 100c14 controls a feature of the integrated GPU's memory interface
cal...
2014 Oct 03
1
[PATCH v2 1/2] drm/nouveau/fb/nv50: Add PFB writes
...0.c
index 4150b0d..5c84d13 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c
@@ -289,6 +289,17 @@ nv50_fb_init(struct nouveau_object *object)
if (ret)
return ret;
+ /* Not a clue what this is exactly. Without enabling bit 1 of
+ * 100c14, system will lockup while initialising the card
+ * (#27501)
+ */
+ if (nv_device(priv)->chipset == 0xac) {
+ if ((nv_rd32(priv, 0x100c14) & 0x00000002) == 0x00000000) {
+ nv_wr32(priv, 0x100c1c, priv->r100c08 >> 8);
+ nv_mask(priv, 0x100c14, 0x00000000, 0x00000002);
+ }
+ }...
2014 Oct 21
0
Questions about some PFB registers on NVAC cards
...an 9400M (NVAC) card,
a PFIFO interrupt 0x00400000 is thrown during the initialisation of that card
(sometime after PFIFO and PGRAPH initialisation) and the laptop will lockup [1],
forcing users to load Nouveau without acceleration.
After some investigation, I found that enabling bit 1 of register 100c14 fixes
the issue on that card. Other NVAC cards are working great without that trick,
and it seems they have that bit enabled by default. What is the role of that
bit, and when should it be turned on?
Before enabling 100c14's bit 1, the Nvidia driver writes some value into 100c1c.
Leaving the d...