search for: 1008r

...vreg36:sel_z<def> = COPY %vreg5<kill>; R600_Reg128:%vreg36 R600_Reg32:%vreg5 register: %vreg36 replace range with [976r,992r:1) RESULT: [976r,992r:1)[992r,1024r:0)  0 at 992r 1 at 976r 1008B%vreg37<def> = COPY %vreg6:sel_w; R600_Reg32:%vreg37 R600_Reg128:%vreg6 register: %vreg37 +[1008r,1040r:0) 1024B%vreg10<def> = COPY %vreg36<kill>; R600_Reg128:%vreg10,%vreg36 register: %vreg10 +[1024r,1120r:0) 1040B%vreg10:sel_w<def> = COPY %vreg37<kill>; R600_Reg128:%vreg10 R600_Reg32:%vreg37 register: %vreg10 replace range with [1024r,1040r:1) RESULT: [1024r,1040r:1)[1...

...reg5<kill>; R600_Reg128:%vreg36 > R600_Reg32:%vreg5 > register: %vreg36 replace range with [976r,992r:1) RESULT: > [976r,992r:1)[992r,1024r:0)  0 at 992r 1 at 976r > 1008B%vreg37<def> = COPY %vreg6:sel_w; R600_Reg32:%vreg37 > R600_Reg128:%vreg6 > register: %vreg37 +[1008r,1040r:0) > 1024B%vreg10<def> = COPY %vreg36<kill>; R600_Reg128:%vreg10,%vreg36 > register: %vreg10 +[1024r,1120r:0) > 1040B%vreg10:sel_w<def> = COPY %vreg37<kill>; R600_Reg128:%vreg10 > R600_Reg32:%vreg37 > register: %vreg10 replace range with [1024r,1040r:1)...

Hi Vincent, On 24/10/2012 23:26, Vincent Lejeune wrote: > Hi, > > I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below. > > The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is : > > // BEFORE LOOP >

Hi, I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below. The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is : // BEFORE LOOP ... Some COPYs.... 400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2