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100048
2008 Oct 24
2
[LLVMdev] SetCC tablegen pattern
I am attempting to match setcc using tablegen w/ the following
patterns:
def FEQ : Instruction<(outs GPRF32:$dst), (ins GPRF32:$src0,
GPRF32:$src1), "eq $dst, $src0, $src1", [(set GPRF32:$dst, (seteq
GPRF32:$src0, GPRF32:$src1))]>;
And it is failing stating that the result must be an integer. Is there a
way around this other than modifying TargetSelectionDAG.td? Also,