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100025
2008 Oct 15
2
[LLVMdev] Forcing basic blocks to end with no more than one branch instruction?
I'm analyzing the basic blocks of MachineInstructions that LLVM
generates for my TargetMachine to try to reconstruct high-level flow
control.
I misunderstood the isTerminator property of an instruction to mean
that it had to be at the end of a basic block, but now I've seen
blocks that end with a conditional branch followed by an unconditional
branch.
I'm sure this depends