search for: 0xc58

...rs/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c > @@ -23,39 +23,65 @@ > #include "acr.h" > #include "gm200.h" > > -#define TEGRA210_MC_BASE 0x70019000 > - > #ifdef CONFIG_ARCH_TEGRA > -#define MC_SECURITY_CARVEOUT2_CFG0 0xc58 > -#define MC_SECURITY_CARVEOUT2_BOM_0 0xc5c > -#define MC_SECURITY_CARVEOUT2_BOM_HI_0 0xc60 > -#define MC_SECURITY_CARVEOUT2_SIZE_128K 0xc64 > -#define TEGRA_MC_SECURITY_CARVEOUT_CFG_LOCKED (1 << 1) > /** > * gm20b_secboot_tegra_read_wp...

...--- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c @@ -23,39 +23,65 @@ #include "acr.h" #include "gm200.h" -#define TEGRA210_MC_BASE 0x70019000 - #ifdef CONFIG_ARCH_TEGRA -#define MC_SECURITY_CARVEOUT2_CFG0 0xc58 -#define MC_SECURITY_CARVEOUT2_BOM_0 0xc5c -#define MC_SECURITY_CARVEOUT2_BOM_HI_0 0xc60 -#define MC_SECURITY_CARVEOUT2_SIZE_128K 0xc64 -#define TEGRA_MC_SECURITY_CARVEOUT_CFG_LOCKED (1 << 1) /** * gm20b_secboot_tegra_read_wpr() - read the WPR registers on Tegra * - * On dGPU, we can...

...m20b.c > > @@ -23,39 +23,65 @@ > > #include "acr.h" > > #include "gm200.h" > > > > -#define TEGRA210_MC_BASE 0x70019000 > > - > > #ifdef CONFIG_ARCH_TEGRA > > -#define MC_SECURITY_CARVEOUT2_CFG0 0xc58 > > -#define MC_SECURITY_CARVEOUT2_BOM_0 0xc5c > > -#define MC_SECURITY_CARVEOUT2_BOM_HI_0 0xc60 > > -#define MC_SECURITY_CARVEOUT2_SIZE_128K 0xc64 > > -#define TEGRA_MC_SECURITY_CARVEOUT_CFG_LOCKED (1 << 1) > > /** > >...

From: Thierry Reding <treding at nvidia.com> Hi, the GPU on Jetson TX2 (GP10B) does not work properly on all devices. Why exactly is not clear, but there are slight differences between the SKUs that were tested. It turns out that the biggest issue is that on some devices (e.g. the one that I have), pulsing the GPU reset twice as is done in the current code (once as part of the power-ungate

From: Thierry Reding <treding at nvidia.com> Hi Ben, here's a revised subset of the patches I had sent out a couple of weeks ago. I've reworked the BAR2 accesses in the way that you had suggested, which at least for GP10B turned out to be fairly trivial to do. I have not looked in detail at this for GV11B yet, but a cursory look showed that BAR2 is accessed in more places, so the

From: Thierry Reding <treding at nvidia.com> Hi Ben, here's a revised subset of the patches I had sent out a couple of weeks ago. I've reworked the BAR2 accesses in the way that you had suggested, which at least for GP10B turned out to be fairly trivial to do. I have not looked in detail at this for GV11B yet, but a cursory look showed that BAR2 is accessed in more places, so the

GP10B is the chip used in Tegra X2 SoCs. This patchset adds support for its base engines after reworking secboot a bit to accomodate its calling convention better. This patchset has been tested rendering simple off-screen buffers using Mesa and yielded the expected result. Alexandre Courbot (15): secboot: allow to boot multiple falcons secboot: pass instance to LS firmware loaders secboot:

This is a highly changed revision of the first patch series that adds secure boot support to Nouveau. This code still depends on NVIDIA releasing official firmware files, but the files released with SHIELD TV and Pixel C can already be used on a Jetson TX1. As you know we are working hard to release the official firmware files, however in the meantime it doesn't hurt to review the code so it

New version of the secure boot code that works with the blobs just merged into linux-firmware. Since the required Mesa patches are also merged, this set is the last piece of the puzzle to get out-of-the-box accelerated Maxwell 2. The basic code remains the same, with a few improvements with respect to how secure falcons are started. Hopefully the patchset is better split too. I have a