Displaying 5 results from an estimated 5 matches for "0x1abcd".
2018 Mar 02
4
generating multiple instructions for a single pattern
Hi All,
I am working on a target which requires to generated two
instructions for a single branch instruction.
ex:
imm 1
br r4,0xabcd
branch address is 0x1abcd, imm has the upper 16 bits and br has
lower 16 bits.
Can anyone let me know how to write these kind of patterns in the
InstrInfo.td file.
Thanks in Advance,
Nagaraju
2018 Mar 02
0
generating multiple instructions for a single pattern
On 2 Mar 2018, at 11:09, Nagaraju Mekala via llvm-dev <llvm-dev at lists.llvm.org> wrote:
>
> I am working on a target which requires to generated two
> instructions for a single branch instruction.
> ex:
> imm 1
> br r4,0xabcd
> branch address is 0x1abcd, imm has the upper 16 bits and br has
> lower 16 bits.
>
> Can anyone let me know how to write these kind of patterns in the
> InstrInfo.td file.
Do the two instructions need to be together? Is one providing an operand via an implicit register?
If the two are simply a sequence that...
2018 Mar 02
0
generating multiple instructions for a single pattern
...ar 2, 2018 at 4:39 PM, Nagaraju Mekala via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> Hi All,
>
> I am working on a target which requires to generated two
> instructions for a single branch instruction.
> ex:
> imm 1
> br r4,0xabcd
> branch address is 0x1abcd, imm has the upper 16 bits and br has
> lower 16 bits.
>
> Can anyone let me know how to write these kind of patterns in the
> InstrInfo.td file.
>
> Thanks in Advance,
> Nagaraju
> _______________________________________________
> LLVM Developers mailing list
> llvm...
2018 Mar 02
1
generating multiple instructions for a single pattern
...a llvm-dev <
> llvm-dev at lists.llvm.org> wrote:
>
>> Hi All,
>>
>> I am working on a target which requires to generated two
>> instructions for a single branch instruction.
>> ex:
>> imm 1
>> br r4,0xabcd
>> branch address is 0x1abcd, imm has the upper 16 bits and br has
>> lower 16 bits.
>>
>> Can anyone let me know how to write these kind of patterns in the
>> InstrInfo.td file.
>>
>> Thanks in Advance,
>> Nagaraju
>> _______________________________________________
>> LL...
2018 Mar 02
2
generating multiple instructions for a single pattern
...18, at 11:09, Nagaraju Mekala via llvm-dev <llvm-dev at lists.llvm.org> wrote:
>>
>> I am working on a target which requires to generated two
>> instructions for a single branch instruction.
>> ex:
>> imm 1
>> br r4,0xabcd
>> branch address is 0x1abcd, imm has the upper 16 bits and br has
>> lower 16 bits.
>>
>> Can anyone let me know how to write these kind of patterns in the
>> InstrInfo.td file.
>
> Do the two instructions need to be together? Is one providing an operand via an implicit register?
>
> If t...