search for: 0x1234

Displaying 20 results from an estimated 53 matches for "0x1234".

2009 Jan 19
2
[LLVMdev] HazardRecognizer and RegisterAllocation
...a quite straight-forward RISC, but it does not have hardware interlocks, i.e. data hazards involving memory access must be resolved by the compiler, either by scheduling unrelated instructions or by inserting NOOPs into the load delay slots: ---- For example, code which looks like that: load 0x1234, reg1 noop noop add reg1, 1 load 0x1236, reg2 can be safely transformed to: load 0x1234, reg1 load 0x1236, reg2 noop add reg1, 1 ---- It pleased us quite a lot when we found the HazardRecognizer-class. Without much effort we could assist LLVM to transform code like shown above (with simple (SDU...
2015 May 06
3
[LLVMdev] LLD improvement plan
...eir own sections >> > and >> > then use the linker script to place the sections at the required >> > addresses. >> > How would this be accomplished without linker scripts? >> > >> > >> > I’d prefer to use an "__attribute__((address(0x1234)))” myself. That >> > way >> > you can control platform specifics with #ifdefs. >> >> But that way you have to do layout by hand in C. Generally you won't >> know the size of the preceding code or data so you won't know what >> address to put thing...
2009 Jan 19
0
[LLVMdev] HazardRecognizer and RegisterAllocation
...t have > hardware interlocks, i.e. data hazards involving memory access must be > resolved by the compiler, either by scheduling unrelated > instructions or > by inserting NOOPs into the load delay slots: > > ---- > > For example, code which looks like that: > > load 0x1234, reg1 > noop > noop > add reg1, 1 > load 0x1236, reg2 > > can be safely transformed to: > > load 0x1234, reg1 > load 0x1236, reg2 > noop > add reg1, 1 > > ---- > > It pleased us quite a lot when we found the HazardRecognizer-class. > Without much effo...
2018 Mar 07
1
TLD instruction usage in non-linked sampler mode
...y-odd rule around sRGB conversion. I don't remember what it is, but it feels like this would potentially make it impossible to follow. But I guess going back in time and fixing the hw is also difficult. Can you confirm whether it will always look at slot 0, even in LINKED_TSC mode (i.e. method 0x1234 == 1)? We don't currently make use of that mode in nouveau, but I'm thinking about doing it on Tesla / Fermi so that we can get more than 16 textures per stage on there. Thanks again for the info! -ilia On Wed, Mar 7, 2018 at 3:21 PM, Andy Ritger <aritger at nvidia.com> wrote: &g...
2015 May 06
4
[LLVMdev] LLD improvement plan
...se > __attribute__((section(""))) to place the symbols in their own sections and > then use the linker script to place the sections at the required addresses. > How would this be accomplished without linker scripts? > > > I’d prefer to use an "__attribute__((address(0x1234)))” myself. That way > you can control platform specifics with #ifdefs. But that way you have to do layout by hand in C. Generally you won't know the size of the preceding code or data so you won't know what address to put things at at the granularity of a single C level object/functio...
2018 Feb 06
3
[RFC] Add mergeable and eh_frame section pieces to map files and --print-gc/icf-sections reports
...ugging and analysis as required. Our proposal is to give these pieces special names, which indicate their offset and input section. An example in --print-gc-sections output might be something like: > ld.lld test.o -o test.elf --gc-sections --print-gc-sections “removing section piece ‘.eh_frame+0x1234’ from file ‘test.o’” “removing section piece ‘.rodata.str1.1+0x1234’ from file ‘test.o’” A map file reference would look the same as for other input sections, but again with a reference to the offset within the section. At the moment, such pieces are not mentioned in the print-gc-sections outp...
2009 Jan 19
3
[LLVMdev] HazardRecognizer and RegisterAllocation
Hi Evan, thanks for your response. On Mon, 19 Jan 2009, Evan Cheng wrote: >> For example, code which looks like that: >> >> load 0x1234, reg1 >> noop >> noop >> add reg1, 1 >> load 0x1236, reg2 >> >> can be safely transformed to: >> >> load 0x1234, reg1 >> load 0x1236, reg2 >> noop >> add reg1, 1 >> > The register allocator doesn't reschedule code. It c...
2018 Aug 31
2
Inline ASM ARM syntax to load immediate values with integrated assembler
Hi, What would be the proper syntax in a C file, using inline assembly, to load a immediate value into an ARM register using clang & integrated assembler? The following syntax is rejected by LLVM: // clang -target armv7em-none-eabi -mthumb #define CONSTANT 0x1234 void __attribute__((naked)) foo(void) { asm volatile ( "ldr r0, =%0 \n" : : "X" (CONSTANT) : "r0" ); } “X” transforms the constant into a “#1234”, and LLVM does not seem to acc...
2007 Jul 20
1
reboot from com32
Q: Is there a way to do a reboot (either warm or cold) from a com32 program? I have a com32 program that sometimes (based upon conditions) needs to reboot the system. I would prefer to do a warm reboot (40:72 = 0x1234), but at this point cold would be OK too. grepping through syslinux-3.51 I only found one reference, in iso/pxelinux.asm at the tail end of 'kaboom' ... but presumably that only happens after things go wrong. It isn't clear to me how to do this since the com32 program is running in 32...
2018 Feb 06
0
[RFC] Add mergeable and eh_frame section pieces to map files and --print-gc/icf-sections reports
...red. Our proposal is to give these pieces special names, which > indicate their offset and input section. An example in --print-gc-sections > output might be something like: > > > ld.lld test.o -o test.elf --gc-sections --print-gc-sections > > “removing section piece ‘.eh_frame+0x1234’ from file ‘test.o’” > > “removing section piece ‘.rodata.str1.1+0x1234’ from file ‘test.o’” > > A map file reference would look the same as for other input sections, but > again with a reference to the offset within the section. > > > > At the moment, such pieces are not...
2018 Mar 02
2
TLD instruction usage in non-linked sampler mode
...quite as sure due to the bindless nature. I've been trying to understand how the TLD operation works (which is used to implement texelFetch in GLSL). It does not appear to the op takes an explicit sampler id at all (unlike all the other texturing operations). In unlinked TSC mode (i.e. method 0x1234 == 0), my observation is that it desperately wants for a valid sampler to be bound to sampler slot 0. Of course I don't think TLD actually needs anything from the sampler, which makes this all the more odd. Is that a correct assessment of the operation of the TLD instruction? Is there any way...
2011 Apr 26
2
[LLVMdev] Symbol folding with MC
...nt to know if there's a better way to do this, instead of delaying it to the stage of MCInst lowering. The other questions is how to fold single and complex operations on symbols, say we have something like: unsigned int g_var[80]; unsigned int foo() { return (unsigned int)&g_var[0] & 0x1234; } Currently this moves the g_var address into a register and then performs the and operation, but i want this to be done at compilation time, so we have something like: move retreg, (g_val & 0x1234) Without touching anything else only additions get folded, but this could be expanded into ot...
2012 Jul 18
1
Attaching usb devices
Is the only way to attach a usb device to a vm first specifying the device, <hostdev mode='subsystem' type='usb' managed='no'> <source> <vendor id='0x3080'/> <product id='0x1234'/> </source> </hostdev> and then booting the vm while the device is attached? Can't I attach/detach a USB device to the vm later? I did try the method suggested in http://david.wragg.org/blog/2009/03/usb-pass-through-with-libvirt-and-kvm.html but did not hav...
2005 Sep 09
1
bochs or qemu & gdb
HPA, now that syslinux release madness has calmed down, could you provide some info on how we syslinux-minions/wannabes can use bochs and/or qemu to run (sys|pxe|iso|ext)linux in an emulated environment thats more conducive to debugging, single-stepping, and ultimately understanding how the magic happens ? tia jimc
2020 May 22
2
RFC: Add DWARF support for yaml2obj
...thout having to specify the exact DW_FORM. Sometimes, we might even end up in an ambiguous situation and not get the result we want. For example, in DWARFv4, the DW_AT_high_pc attribute has either a Constant or an Address class, which use completely different forms, but if we have just "Value: 0x1234", which is it? In DWARFv3, it is always an Address, if I remember correctly, so in that case, we might want our default to be "Address". However, for DWARFv4 the compiler typically emits DW_AT_high_pc using a Constant form, and most people might expect that to be used instead. I thi...
2015 May 06
2
[LLVMdev] LLD improvement plan
> > > Linker scripts are worse than everything - except for the alternatives > that > > we know about. Any particular suggestions here? > > I very much care about the functionality provided by linker scripts (for > embedded systems and kernel work), but I do agree that most current > script formats are hard to use, debug, reason about, etc... I have > often
2017 Feb 24
0
[PATCH 1/5] PCI: Recognize Thunderbolt devices
Detect on probe whether a PCI device is part of a Thunderbolt controller. Intel uses a Vendor-Specific Extended Capability (VSEC) with ID 0x1234 on such devices. Detect presence of this VSEC and cache it in a newly added is_thunderbolt bit in struct pci_dev. Add a helper to check whether a given PCI device is situated on a Thunderbolt daisy chain. The necessity arises from the following: * To power off Thunderbolt controllers on Macs ev...
2016 Mar 30
2
[cfe-dev] RFC: Up front type information generation in clang and llvm
...talked >> about when writing all of this down. :) >> >> Basically to handle abbreviations you can do them the similarly to types >> by creating a blob with an index/hash/etc and then reference that as part >> of the type tuple, e.g.: >> >> $1 = { DIAbbrev: 0x1234, DIBlob: <blah> } >> $2 = { DIType: <ID>, DIAbbrev: $1, DIBlob: <blah> } >> >> and keep them uniqued during emission and remember to merge these as well >> during module merge time. >> > > Makes sense, but wouldn't you need multiple abbrevia...
2011 Apr 26
0
[LLVMdev] Symbol folding with MC
...tions as necessary. This would all be at the MachineInstr level before lowering to MC. > The other questions is how to fold single and complex operations on symbols, say we have something like: > > unsigned int g_var[80]; > unsigned int foo() { return (unsigned int)&g_var[0] & 0x1234; } > > Currently this moves the g_var address into a register and then performs the and operation, but i want this to be done at compilation time, so we have something like: > > move retreg, (g_val & 0x1234) > For many targets this isn't legal, as the object file format u...
2016 Mar 30
0
[cfe-dev] RFC: Up front type information generation in clang and llvm
...forgetting something I'd talked > about when writing all of this down. :) > > Basically to handle abbreviations you can do them the similarly to types > by creating a blob with an index/hash/etc and then reference that as part > of the type tuple, e.g.: > > $1 = { DIAbbrev: 0x1234, DIBlob: <blah> } > $2 = { DIType: <ID>, DIAbbrev: $1, DIBlob: <blah> } > > and keep them uniqued during emission and remember to merge these as well > during module merge time. > Makes sense, but wouldn't you need multiple abbreviations for each DIType, in ord...