search for: 0x020c

...ing inconsistencies that were more obvious, the worse part is probably between nv30 and nv40. But not sure about that one, if 0x20c is the same method or a different one. nv10 <reg32 offset="0x0208" name="RT_FORMAT" type="bitfield"> <reg32 offset="0x020c" name="RT_PITCH" type="bitfield"> <reg32 offset="0x0210" name="COLOR_OFFSET" type="hexa"/> <reg32 offset="0x0214" name="ZETA_OFFSET" type="hexa"/> nv20 <reg32 offset="0x0208"...

...return ret; > > - nv_wo32(mem, 0x0200, lower_32_bits(priv->bar[0].pgd->addr)); > - nv_wo32(mem, 0x0204, upper_32_bits(priv->bar[0].pgd->addr)); > - nv_wo32(mem, 0x0208, lower_32_bits(nv_device_resource_len(device, 3) - 1)); > - nv_wo32(mem, 0x020c, upper_32_bits(nv_device_resource_len(device, 3) - 1)); > + nv_wo32(mem, 0x0200, lower_32_bits(priv->bar[nr].pgd->addr)); > + nv_wo32(mem, 0x0204, upper_32_bits(priv->bar[nr].pgd->addr)); > + nv_wo32(mem, 0x0208, lower_32_bits(bar_len - 1)); > + nv_wo...

...; nouveau_vm_ref(NULL, &vm, NULL); if (ret) return ret; - nv_wo32(mem, 0x0200, lower_32_bits(priv->bar[0].pgd->addr)); - nv_wo32(mem, 0x0204, upper_32_bits(priv->bar[0].pgd->addr)); - nv_wo32(mem, 0x0208, lower_32_bits(nv_device_resource_len(device, 3) - 1)); - nv_wo32(mem, 0x020c, upper_32_bits(nv_device_resource_len(device, 3) - 1)); + nv_wo32(mem, 0x0200, lower_32_bits(priv->bar[nr].pgd->addr)); + nv_wo32(mem, 0x0204, upper_32_bits(priv->bar[nr].pgd->addr)); + nv_wo32(mem, 0x0208, lower_32_bits(bar_len - 1)); + nv_wo32(mem, 0x020c, upper_32_bits(bar_len - 1));...

This patch fixes two issues in nv40_miptree_layout. First, pt->width0 is used, which is the size of the whole texture, while width, which is the size of the mipmap level, should be used. Second, the current code does not 64-byte align the pitch of swizzled textures. However, on my NV40 this causes a pgraph error regarding the pitch register (and sometimes a system lockup too), which is fixed

...; nouveau_vm_ref(NULL, &vm, NULL); if (ret) return ret; - nv_wo32(mem, 0x0200, lower_32_bits(priv->bar[0].pgd->addr)); - nv_wo32(mem, 0x0204, upper_32_bits(priv->bar[0].pgd->addr)); - nv_wo32(mem, 0x0208, lower_32_bits(nv_device_resource_len(device, 3) - 1)); - nv_wo32(mem, 0x020c, upper_32_bits(nv_device_resource_len(device, 3) - 1)); + nv_wo32(mem, 0x0200, lower_32_bits(priv->bar[nr].pgd->addr)); + nv_wo32(mem, 0x0204, upper_32_bits(priv->bar[nr].pgd->addr)); + nv_wo32(mem, 0x0208, lower_32_bits(bar_len - 1)); + nv_wo32(mem, 0x020c, upper_32_bits(bar_len - 1));...

...vc0_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine, nv_wo32(mem, 0x0200, lower_32_bits(priv->bar[0].pgd->addr)); nv_wo32(mem, 0x0204, upper_32_bits(priv->bar[0].pgd->addr)); - nv_wo32(mem, 0x0208, lower_32_bits(pci_resource_len(pdev, 3) - 1)); - nv_wo32(mem, 0x020c, upper_32_bits(pci_resource_len(pdev, 3) - 1)); + nv_wo32(mem, 0x0208, lower_32_bits(nv_device_resource_len(device, 3) - 1)); + nv_wo32(mem, 0x020c, upper_32_bits(nv_device_resource_len(device, 3) - 1)); /* BAR1 */ ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0, 0, @@ -143,7 +142,7...

Hello everyone, GK20A is the Kepler-based GPU used in the upcoming Tegra K1 chips. The following patches perform architectural changes to Nouveau that are necessary to support non-PCI GPUs and add initial support for GK20A. Although the support is still very basic and more user-space changes will be needed to make the full graphics stack run on top of it, we were able to successfully open

...ADD(dev, SW, &psw->base.base); NVOBJ_CLASS(dev, 0x906e, SW); + NVOBJ_MTHD (dev, 0x906e, 0x0200, nvc0_swmthd_vblsem_offset_high); + NVOBJ_MTHD (dev, 0x906e, 0x0204, nvc0_swmthd_vblsem_offset_low); + NVOBJ_MTHD (dev, 0x906e, 0x0208, nvc0_swmthd_vblsem_release_val); + NVOBJ_MTHD (dev, 0x906e, 0x020c, nvc0_swmthd_vblsem_release); + NVOBJ_MTHD (dev, 0x906e, 0x0210, nvc0_swmthd_page_flip); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvd0_display.c b/drivers/gpu/drm/nouveau/nvd0_display.c index dac525b..2985a5a 100644 --- a/drivers/gpu/drm/nouveau/nvd0_display.c +++ b/drivers/gpu/drm/nouve...

On 12/02/14 05:38, Alexandre Courbot wrote: > Upcoming mobile Kepler GPUs (such as GK20A) use the platform bus instead > of PCI to which Nouveau is tightly dependent. This patch allows Nouveau > to handle platform devices by: > > - abstracting PCI-dependent functions that were typically used for > resource querying and page mapping, > - introducing a nv_device_is_pci()

On Mon, Feb 10, 2014 at 8:50 PM, Thierry Reding <thierry.reding at gmail.com> wrote: > On Mon, Feb 10, 2014 at 02:53:00PM +0900, Alexandre Courbot wrote: > [...] >> diff --git a/drivers/gpu/drm/nouveau/core/engine/device/base.c b/drivers/gpu/drm/nouveau/core/engine/device/base.c > [...] >> +resource_size_t >> +nv_device_resource_start(struct nouveau_device *device,

...vc0_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine, nv_wo32(mem, 0x0200, lower_32_bits(priv->bar[0].pgd->addr)); nv_wo32(mem, 0x0204, upper_32_bits(priv->bar[0].pgd->addr)); - nv_wo32(mem, 0x0208, lower_32_bits(pci_resource_len(pdev, 3) - 1)); - nv_wo32(mem, 0x020c, upper_32_bits(pci_resource_len(pdev, 3) - 1)); + nv_wo32(mem, 0x0208, lower_32_bits(nv_device_resource_len(device, 3) - 1)); + nv_wo32(mem, 0x020c, upper_32_bits(nv_device_resource_len(device, 3) - 1)); /* BAR1 */ ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0, 0, @@ -143,7 +142,7...

Latest patches for GK20A, taking comments received for v3 into account. Changes since v3: - use only pfn_to_page() and page_to_pfn() in GK20A's FB. These functions are present on every arch and the physical address to page frame number conversion is also consistently a shift of PAGE_SHIFT. This part will probably be replaced by something nicer in the future anyway. - fixed a warning on

Hi everyone, Way overdue v2 of the final patches that enable basic GK20A support. Hopefully all the issues raised with v1 have been addressed. Changes since v1: - Use gk20a clock driver by Ben instead of twiddling nv04's - Name new classes after gk20a instead of nvea - Addressed comments about BAR initialization code factorization - Removed non-essential code which only purpose was to avoid

Changes since v2: - Enabled software class - Removed unneeded changes to nouveau_accel_init() - Replaced use of architecture-private pfn_to_dma() and dma_to_pfn() with the portable page_to_phys()/phys_to_page() - Fixed incorrect comment/commit log talking about bytes instead of words Hope this looks good! Once this gets merged the next set will be to use this driver on Jetson and Venice2

...d); + if (ret) + return ret; + + /*update pgd in inst blk */ + nv_wo32(pmuvm->mem, 0x0200, lower_32_bits(pmuvm->pgd->addr)); + nv_wo32(pmuvm->mem, 0x0204, upper_32_bits(pmuvm->pgd->addr)); + nv_wo32(pmuvm->mem, 0x0208, lower_32_bits(pmu_area_len - 1)); + nv_wo32(pmuvm->mem, 0x020c, upper_32_bits(pmu_area_len - 1)); + + /* allocate memory for pmu fw to be copied to*/ + ret = nvkm_gpuobj_new(nv_object(priv), NULL, GK20A_PMU_UCODE_SIZE_MAX, + 0x1000, 0, &priv->ucode.obj); + if (ret) + return ret; + + ucode_image = (u32 *)((u8 *)desc + desc->descriptor_size);...

This patchset applies some minor fixes to renouveau.xml and then unifies the nv30 and nv40 register definitions. nv30 and nv40 are very similar and have the same offsets for the registers they share. The major differences are: 1. Texture setup is different due to full NPOT support on nv40 2. More advanced blending/render targets on nv40 3. NV30 has fixed function registers, which NV40 lacks The

Hi everyone, Here is the second batch of patches to add GK20A support to Nouveau. This time we are adding the actual chip support, and this series brings the driver to a point where a slightly-tweaked Mesa successfully runs shaders and renders triangles on GBM! Many thanks to Thierry Reding and the people on the #nouveau IRC channel for their help without which we would not have reached this

...) + goto fw_alloc_err; + + /*update pgd in inst blk */ + nv_wo32(ppmuvm->mem, 0x0200, lower_32_bits(ppmuvm->pgd->addr)); + nv_wo32(ppmuvm->mem, 0x0204, upper_32_bits(ppmuvm->pgd->addr)); + nv_wo32(ppmuvm->mem, 0x0208, lower_32_bits(pmu_area_len - 1)); + nv_wo32(ppmuvm->mem, 0x020c, upper_32_bits(pmu_area_len - 1)); + + /* allocate memory for pmu fw to be copied to*/ + ret = nvkm_gpuobj_new(nv_object(ppmu), NULL, + GK20A_PMU_UCODE_SIZE_MAX, 0x1000, 0, &pmu->ucode.obj); + if (ret) + goto fw_alloc_err; + + ucode_image = (u32 *)((u8 *)desc + desc->descriptor_size)...

.../ >> + nv_wo32(pmuvm->mem, 0x0200, lower_32_bits(pmuvm->pgd->addr)); >> + nv_wo32(pmuvm->mem, 0x0204, upper_32_bits(pmuvm->pgd->addr)); >> + nv_wo32(pmuvm->mem, 0x0208, lower_32_bits(pmu_area_len - 1)); >> + nv_wo32(pmuvm->mem, 0x020c, upper_32_bits(pmu_area_len - 1)); >> + >> + /* allocate memory for pmu fw to be copied to*/ >> + ret = nvkm_gpuobj_new(nv_object(priv), NULL, >> GK20A_PMU_UCODE_SIZE_MAX, >> + 0x1000, 0, &priv->ucode.obj); >> +...

...0, - 0x03e8eeec, - 0x0144d7f1, - 0xf500d3f0, -/* 0x01e3: ticks_from_ns_quit */ - 0xb903a821, - 0xb0fc02ce, - 0x00f8c0fc, -/* 0x01ec: ticks_from_us */ - 0xb0f9c0f9, - 0x0144d7f1, - 0xf500d3f0, - 0xb903a821, - 0xb4b002ce, - 0x050bf400, -/* 0x0206: ticks_from_us_quit */ - 0xb0fce4bd, - 0x00f8c0fc, -/* 0x020c: ticks_to_us */ - 0x0144d7f1, - 0xff00d3f0, - 0x00f8eced, -/* 0x0218: timer */ - 0x80f990f9, - 0x981032f4, - 0x86b003f8, - 0x531cf400, - 0x07f084bd, - 0x0008d038, - 0x87f004bd, - 0x0088cf34, - 0xbb9a0998, - 0xe9bb0298, - 0x03fe8000, - 0xcf0887f0, - 0x84f00088, - 0x201bf402, - 0xcf3487f0, - 0xe0b800...