Displaying 5 results from an estimated 5 matches for "0x01fff000".
2014 Dec 31
0
[PATCH 2/2] nvc0: regenerate rnndb headers
...__LEN 0x00000005
-#define NVC0_3D_BIND_TSC_ACTIVE 0x00000001
+#define NVC0_3D_BIND_TSC_ACTIVE 0x00000001
#define NVC0_3D_BIND_TSC_SAMPLER__MASK 0x00000ff0
-#define NVC0_3D_BIND_TSC_SAMPLER__SHIFT 4
+#define NVC0_3D_BIND_TSC_SAMPLER__SHIFT 4
#define NVC0_3D_BIND_TSC_TSC__MASK 0x01fff000
#define NVC0_3D_BIND_TSC_TSC__SHIFT 12
#define NVC0_3D_BIND_TIC(i0) (0x00002404 + 0x20*(i0))
-#define NVC0_3D_BIND_TIC__ESIZE 0x00000020
+#define NVC0_3D_BIND_TIC__ESIZE 0x00000020
#define NVC0_3D_BIND_TIC__LEN 0x00000005
-#define NVC0_3D_BIND_TIC_ACTIVE 0x00000001...
2016 Oct 16
10
[PATCH 1/5] hwdefs: update nvc0_3d, add gm107_texture for new TIC format
...__LEN 0x00000005
-#define NVC0_3D_BIND_TSC_ACTIVE 0x00000001
+#define NVC0_3D_BIND_TSC_ACTIVE 0x00000001
#define NVC0_3D_BIND_TSC_SAMPLER__MASK 0x00000ff0
-#define NVC0_3D_BIND_TSC_SAMPLER__SHIFT 4
+#define NVC0_3D_BIND_TSC_SAMPLER__SHIFT 4
#define NVC0_3D_BIND_TSC_TSC__MASK 0x01fff000
#define NVC0_3D_BIND_TSC_TSC__SHIFT 12
#define NVC0_3D_BIND_TIC(i0) (0x00002404 + 0x20*(i0))
-#define NVC0_3D_BIND_TIC__ESIZE 0x00000020
+#define NVC0_3D_BIND_TIC__ESIZE 0x00000020
#define NVC0_3D_BIND_TIC__LEN 0x00000005
-#define NVC0_3D_BIND_TIC_ACTIVE 0x00000001...
2014 Dec 31
2
[PATCH 1/2] nv50: regenerate rnndb headers
The headers hadn't been regenerated in a long time, and there were a few
minor divergences. Among other things, rnndb has changed naming to
G80/etc, for now I've not tackled switching that over and manually
replaced the nvidia codenames back to the chip ids. However no other
modifications of the headergen'd headers was done.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
2016 Oct 27
11
[PATCH v2 0/7] Add Maxwell support
I believe I've addressed all the feedback from the first time around, and
also made fixes necessary for GM20x based on testing results. I believe
now it should actually work for all GM10x and GM20x. Further, GP10x should
be very easy to add, but without someone to actually test I didn't want to
claim support for it.
Ilia Mirkin (7):
exa: add GM10x acceleration support
hwdefs: update
2016 Feb 15
24
[PATCH 01/23] nv50: import updated g80_defs.xml.h from rnndb
From: Ben Skeggs <bskeggs at redhat.com>
Signed-off-by: Ben Skeggs <bskeggs at redhat.com>
---
src/gallium/drivers/nouveau/nv50/g80_defs.xml.h | 279 ++++++++++++++++++++++++
1 file changed, 279 insertions(+)
create mode 100644 src/gallium/drivers/nouveau/nv50/g80_defs.xml.h
diff --git a/src/gallium/drivers/nouveau/nv50/g80_defs.xml.h