Displaying 20 results from an estimated 44 matches for "0x007f".
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0x0070
2014 Feb 19
2
[LLVMdev] [lldb-dev] How is variable info retrieved in debugging for executables generated by llvm backend?
...RM_strp] ( .debug_str[0x000000be] =
> "main")
> 0x00000027: DW_AT_decl_file [DW_FORM_data1] (0x01)
> 0x00000028: DW_AT_decl_line [DW_FORM_data1] (0x02)
> 0x00000029: DW_AT_prototyped [DW_FORM_flag_present] (true)
> 0x00000029: DW_AT_type [DW_FORM_ref4] (cu + 0x007f => {0x0000007f})
> 0x0000002d: DW_AT_external [DW_FORM_flag_present] (true)
> 0x0000002d: DW_AT_low_pc [DW_FORM_addr] (0x0000000000000028)
> 0x00000031: DW_AT_high_pc [DW_FORM_addr] (0x0000000000000084)
> 0x00000035: DW_AT_frame_base [DW_FORM_block1] (<0x02> 90...
2003 Aug 29
1
RC2: Compile errors Solaris 8 (cc) and suggested fix
...- 0x0064,
- 0x0065,
- 0x0066,
- 0x0067,
- 0x0068,
- 0x0069,
- 0x006A,
- 0x006B,
- 0x006C,
- 0x006D,
- 0x006E,
- 0x006F,
- 0x0070,
- 0x0071,
- 0x0072,
- 0x0073,
- 0x0074,
- 0x0075,
- 0x0076,
- 0x0077,
- 0x0078,
- 0x0079,
- 0x007A,
- 0x007B,
- 0x007C,
- 0x007D,
- 0x007E,
- 0x007F,
- 0x00C7,
- 0x00FC,
- 0x00E9,
- 0x00E2,
- 0x00E4,
- 0x00E0,
- 0x00E5,
- 0x00E7,
- 0x00EA,
- 0x00EB,
- 0x00E8,
- 0x00EF,
- 0x00EE,
- 0x00EC,
- 0x00C4,
- 0x00C5,
- 0x00C9,
- 0x00E6,
- 0x00C6,
- 0x00F4,
- 0x00F6,
- 0x00F2,
- 0x00FB,
- 0x00F9,
- 0x00FF,
- 0x00D6,
- 0x00DC,
-...
2014 Feb 18
1
[LLVMdev] [lldb-dev] How is variable info retrieved in debugging for executables generated by llvm backend?
All of this information is contained in the DWARF debug info that you must generate. Are you generating DWARF? If not, you will need to. If so, please attach an example program that contains DWARF and specify which function you are having trouble getting variable information for.
Greg Clayton
On Feb 18, 2014, at 12:44 AM, 杨勇勇 <triple.yang at gmail.com> wrote:
> Hi, all
>
> I
2014 Feb 18
4
[LLVMdev] How is variable info retrieved in debugging for executables generated by llvm backend?
Hi, all
I ported llvm backend and lldb recently. Both tools can basically work.
lldb is able to debug programs in asm style and frame unwinding is OK.
But "frame variable XX" does not work because lldb is not able to determine
the address of
XX from debug info.
Can someone give any clue?
Thanks in advance.
--
杨勇勇 (Yang Yong-Yong)
-------------- next part --------------
An HTML
2014 Aug 17
0
[PATCH 09/10] pwr/fuc: make $r1-$r10 registers callee-saved in kernel.fuc
...00,
- 0x00000000,
- 0x00000000,
};
diff --git a/nvkm/subdev/pwr/fuc/nva3.fuc.h b/nvkm/subdev/pwr/fuc/nva3.fuc.h
index 8e2ddd9..bf808e4 100644
--- a/nvkm/subdev/pwr/fuc/nva3.fuc.h
+++ b/nvkm/subdev/pwr/fuc/nva3.fuc.h
@@ -885,19 +885,22 @@ uint32_t nva3_pwr_code[] = {
0xd4f100dd,
0x1bf47000,
/* 0x007f: nsec */
- 0xf000f8f2,
+ 0xf900f8f2,
+ 0xf080f990,
0x84b62c87,
0x0088cf06,
-/* 0x0088: nsec_loop */
+/* 0x008c: nsec_loop */
0xb62c97f0,
0x99cf0694,
0x0298bb00,
0xf4069eb8,
- 0x00f8f11e,
-/* 0x009c: wait */
+ 0x80fcf11e,
+ 0x00f890fc,
+/* 0x00a4: wait */
+ 0x80f990f9,
0xb62c87f0,
0x...
2020 Oct 28
2
GT710 and Nouveau on ARM/ARM64
...0x030000
[ 1.114404] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x00ffffff]
[ 1.114456] pci 0000:01:00.0: reg 0x14: [mem 0x00000000-0x07ffffff
64bit pref]
[ 1.114510] pci 0000:01:00.0: reg 0x1c: [mem 0x00000000-0x01ffffff
64bit pref]
[ 1.114551] pci 0000:01:00.0: reg 0x24: [io 0x0000-0x007f]
[ 1.114590] pci 0000:01:00.0: reg 0x30: [mem 0x00000000-0x0007ffff pref]
[ 1.114853] pci 0000:01:00.0: 4.000 Gb/s available PCIe bandwidth,
limited by 5.0 GT/s PCIe x1 link at 0000:00:00.0 (capable of 63.008
Gb/s with 8.0 GT/s PCIe x8 link)
[ 1.115022] pci 0000:01:00.0: vgaarb: VGA device...
2020 Nov 03
2
GT710 and Nouveau on ARM/ARM64
...0: [mem 0x00000000-0x00ffffff]
> > [ 1.114456] pci 0000:01:00.0: reg 0x14: [mem 0x00000000-0x07ffffff
> > 64bit pref]
> > [ 1.114510] pci 0000:01:00.0: reg 0x1c: [mem 0x00000000-0x01ffffff
> > 64bit pref]
> > [ 1.114551] pci 0000:01:00.0: reg 0x24: [io 0x0000-0x007f]
> > [ 1.114590] pci 0000:01:00.0: reg 0x30: [mem 0x00000000-0x0007ffff pref]
> > [ 1.114853] pci 0000:01:00.0: 4.000 Gb/s available PCIe bandwidth,
> > limited by 5.0 GT/s PCIe x1 link at 0000:00:00.0 (capable of 63.008
> > Gb/s with 8.0 GT/s PCIe x8 link)
> > [...
2020 May 06
6
GeForce(R) GT 710 1GB PCIE x 1 on arm64
...000:01:00.0: reg 0x10: [mem 0x00000000-0x00ffffff]
> > [ 6.482976] pci 0000:01:00.0: reg 0x14: [mem 0x00000000-0x07ffffff 64bit pref]
> > [ 6.483022] pci 0000:01:00.0: reg 0x1c: [mem 0x00000000-0x01ffffff 64bit pref]
> > [ 6.483056] pci 0000:01:00.0: reg 0x24: [io 0x0000-0x007f]
> > [ 6.483087] pci 0000:01:00.0: reg 0x30: [mem 0x00000000-0x0007ffff pref]
> > [ 6.483313] pci 0000:01:00.0: 4.000 Gb/s available PCIe bandwidth, limited by 5 GT/s x1 link at 0000:00:01.0 (capable of 32.000 Gb/s with 5 GT/s x8 link)
> > [ 6.483463] pci 0000:01:00.0: vg...
2020 Oct 28
0
GT710 and Nouveau on ARM/ARM64
...pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x00ffffff]
> [ 1.114456] pci 0000:01:00.0: reg 0x14: [mem 0x00000000-0x07ffffff
> 64bit pref]
> [ 1.114510] pci 0000:01:00.0: reg 0x1c: [mem 0x00000000-0x01ffffff
> 64bit pref]
> [ 1.114551] pci 0000:01:00.0: reg 0x24: [io 0x0000-0x007f]
> [ 1.114590] pci 0000:01:00.0: reg 0x30: [mem 0x00000000-0x0007ffff pref]
> [ 1.114853] pci 0000:01:00.0: 4.000 Gb/s available PCIe bandwidth,
> limited by 5.0 GT/s PCIe x1 link at 0000:00:00.0 (capable of 63.008
> Gb/s with 8.0 GT/s PCIe x8 link)
> [ 1.115022] pci 0000:01...
2020 May 06
0
GeForce(R) GT 710 1GB PCIE x 1 on arm64
...6.482931] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x00ffffff]
> [ 6.482976] pci 0000:01:00.0: reg 0x14: [mem 0x00000000-0x07ffffff 64bit pref]
> [ 6.483022] pci 0000:01:00.0: reg 0x1c: [mem 0x00000000-0x01ffffff 64bit pref]
> [ 6.483056] pci 0000:01:00.0: reg 0x24: [io 0x0000-0x007f]
> [ 6.483087] pci 0000:01:00.0: reg 0x30: [mem 0x00000000-0x0007ffff pref]
> [ 6.483313] pci 0000:01:00.0: 4.000 Gb/s available PCIe bandwidth, limited by 5 GT/s x1 link at 0000:00:01.0 (capable of 32.000 Gb/s with 5 GT/s x8 link)
> [ 6.483463] pci 0000:01:00.0: vgaarb: VGA devic...
2020 Nov 03
0
GT710 and Nouveau on ARM/ARM64
...ffff]
> > > [ 1.114456] pci 0000:01:00.0: reg 0x14: [mem 0x00000000-0x07ffffff
> > > 64bit pref]
> > > [ 1.114510] pci 0000:01:00.0: reg 0x1c: [mem 0x00000000-0x01ffffff
> > > 64bit pref]
> > > [ 1.114551] pci 0000:01:00.0: reg 0x24: [io 0x0000-0x007f]
> > > [ 1.114590] pci 0000:01:00.0: reg 0x30: [mem 0x00000000-0x0007ffff pref]
> > > [ 1.114853] pci 0000:01:00.0: 4.000 Gb/s available PCIe bandwidth,
> > > limited by 5.0 GT/s PCIe x1 link at 0000:00:00.0 (capable of 63.008
> > > Gb/s with 8.0 GT/s PCIe...
2005 Aug 26
0
NUT patches
...f0d121)
Global Unit Exponent(0x0007)
Feature/48
Global Report ID(0x0031)
Local Usage(0x0030)
Feature/49
Global Report ID(0x0032)
Local Usage(0x0053)
Global Logical Minimum(0x0057)
Global Logical Maximum(0x0061)
Feature/50
Global Report ID(0x0033)
Local Usage(0x0054)
Global Logical Minimum(0x007f)
Global Logical Maximum(0x008b)
Feature/51
Global Report ID(0x0034)
Global Usage Page(0xff86)
Local Usage(0x0024)
Global Logical Minimum(0x00aa)
Global Logical Maximum(0x00fe)
Global Unit(0x0000)
Global Unit Exponent(0x0000)
Feature/52
Global Report ID(0x0035)
Local Usage(0x0061)
Global...
2020 May 06
0
GeForce(R) GT 710 1GB PCIE x 1 on arm64
...g 0x10: [mem 0x00000000-0x00ffffff]
> > > [ 6.482976] pci 0000:01:00.0: reg 0x14: [mem 0x00000000-0x07ffffff 64bit pref]
> > > [ 6.483022] pci 0000:01:00.0: reg 0x1c: [mem 0x00000000-0x01ffffff 64bit pref]
> > > [ 6.483056] pci 0000:01:00.0: reg 0x24: [io 0x0000-0x007f]
> > > [ 6.483087] pci 0000:01:00.0: reg 0x30: [mem 0x00000000-0x0007ffff pref]
> > > [ 6.483313] pci 0000:01:00.0: 4.000 Gb/s available PCIe bandwidth, limited by 5 GT/s x1 link at 0000:00:01.0 (capable of 32.000 Gb/s with 5 GT/s x8 link)
> > > [ 6.483463] pci 0...
2014 Feb 20
2
[LLVMdev] [lldb-dev] How is variable info retrieved in debugging for executables generated by llvm backend?
...quot;main")
> > 0x00000027: DW_AT_decl_file [DW_FORM_data1] (0x01)
> > 0x00000028: DW_AT_decl_line [DW_FORM_data1] (0x02)
> > 0x00000029: DW_AT_prototyped [DW_FORM_flag_present] (true)
> > 0x00000029: DW_AT_type [DW_FORM_ref4] (cu + 0x007f =>
> {0x0000007f})
> > 0x0000002d: DW_AT_external [DW_FORM_flag_present] (true)
> > 0x0000002d: DW_AT_low_pc [DW_FORM_addr] (0x0000000000000028)
> > 0x00000031: DW_AT_high_pc [DW_FORM_addr] (0x0000000000000084)
> > 0x00000035: DW_AT_frame_base [DW_FO...
2020 May 08
0
GeForce(R) GT 710 1GB PCIE x 1 on arm64
...g 0x10: [mem 0x00000000-0x00ffffff]
> > > [ 6.482976] pci 0000:01:00.0: reg 0x14: [mem 0x00000000-0x07ffffff 64bit pref]
> > > [ 6.483022] pci 0000:01:00.0: reg 0x1c: [mem 0x00000000-0x01ffffff 64bit pref]
> > > [ 6.483056] pci 0000:01:00.0: reg 0x24: [io 0x0000-0x007f]
> > > [ 6.483087] pci 0000:01:00.0: reg 0x30: [mem 0x00000000-0x0007ffff pref]
> > > [ 6.483313] pci 0000:01:00.0: 4.000 Gb/s available PCIe bandwidth, limited by 5 GT/s x1 link at 0000:00:01.0 (capable of 32.000 Gb/s with 5 GT/s x8 link)
> > > [ 6.483463] pci 0...
2020 May 06
4
GeForce(R) GT 710 1GB PCIE x 1 on arm64
Hi to all.
I'm experimenting with running a
https://www.zotac.com/us/product/graphics_card/geforce%C2%AE-gt-710-1gb-pcie-x-1
card on an Nvidia Jetson TX2 arm64 device.
Possible?
Linux kernel aarch64 5.6.10.
Because Nvidia did not list drivers for this architecture, I'm
experimenting with a nouveau driver.
The Jetson TX2 has a default driver for the host1x framebuffer for output
from the
2020 Oct 28
2
GT710 and Nouveau on ARM/ARM64
Hi
Seeing as we (Raspberry Pi) have just launched the Compute Module 4
with an exposed PCIe x1 lane, people are asking about adding graphics
cards.
Seeing as you are the people who have the knowledge with regard to
NVidia and nouveau, what are your immediate thoughts of nouveau
working on ARM/ARM64? Is there a chance of this working? I'm no PCIe
expert, although I can call on some expertise
2020 May 14
0
[virtio-dev] [PATCH v3 00/15] virtio-mem: paravirtualized memory
...virtio-mem-pci,id=vm0,memdev=mem1
> qom-set vm0 requested-size 256M
>
> // Go back to the terminal and access file system will got following kernel warning.
> [ 19.515549] pci 0000:00:04.0: [1af4:1015] type 00 class 0x00ff00
> [ 19.516227] pci 0000:00:04.0: reg 0x10: [io 0x0000-0x007f]
> [ 19.517196] pci 0000:00:04.0: BAR 0: assigned [io 0x1000-0x107f]
> [ 19.517843] virtio-pci 0000:00:04.0: enabling device (0000 -> 0001)
> [ 19.535957] PCI Interrupt Link [LNKD] enabled at IRQ 11
> [ 19.536507] virtio-pci 0000:00:04.0: virtio_pci: leaving for legacy drive...
2018 Jan 25
0
Problems getting nouveau to work with either Geforce GT710 or Geforce 9800GT on ARM Cortex-A9
...0x030000
[ 5.094834] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x00ffffff]
[ 5.094846] pci 0000:01:00.0: reg 0x14: [mem 0x00000000-0x0fffffff 64bit pref]
[ 5.094857] pci 0000:01:00.0: reg 0x1c: [mem 0x00000000-0x01ffffff 64bit pref]
[ 5.094865] pci 0000:01:00.0: reg 0x24: [io 0x0000-0x007f]
[ 5.094873] pci 0000:01:00.0: reg 0x30: [mem 0x00000000-0x0007ffff pref]
[ 5.095001] pci 0000:01:00.0: vgaarb: VGA device added: decodes=io+mem,owns=none,locks=none
[ 5.103411] pci 0000:01:00.1: [10de:0fb8] type 00 class 0x040300
[ 5.103432] pci 0000:01:00.1: reg 0x10: [mem 0x00000000-...
2016 Feb 26
0
[PATCH 2/4] pmu/fuc: replace mov+sethi with imm32
...0xf104bd00,
+ 0xb607acd7,
+ 0xddcf06d4,
+ 0x00d4f100,
+ 0xf21bf470,
+ 0x07a4d7f1,
+ 0xcf06d4b6,
+ 0x00f800dd,
+/* 0x0040: wr32 */
+ 0x07a007f1,
+ 0xd00604b6,
+ 0x04bd000e,
+ 0x07a407f1,
0xd00604b6,
0x04bd000d,
-/* 0x006c: wr32_wait */
- 0x07acd7f1,
- 0xcf06d4b6,
- 0xd4f100dd,
- 0x1bf47000,
-/* 0x007f: nsec */
- 0xf900f8f2,
- 0xf080f990,
- 0x84b62c87,
- 0x0088cf06,
-/* 0x008c: nsec_loop */
- 0xb62c97f0,
- 0x99cf0694,
- 0x0298bb00,
- 0xf4069eb8,
- 0x80fcf11e,
- 0x00f890fc,
-/* 0x00a4: wait */
- 0x80f990f9,
- 0xb62c87f0,
- 0x88cf0684,
-/* 0x00b1: wait_loop */
- 0x02eeb900,
- 0xb90421f4,
- 0xadfd02...