Displaying 6 results from an estimated 6 matches for "0x0010a008".
2015 Apr 13
3
[PATCH v4] pmu/gk20a: PMU boot support
..._pmu_intr(struct nvkm_subdev *subdev)
+{
+ struct gk20a_pmu_priv *priv = to_gk20a_priv(nvkm_pmu(subdev));
+ struct nvkm_mc *pmc = nvkm_mc(priv);
+ u32 intr, mask;
+
+ if (!priv->isr_enabled)
+ return;
+
+ mask = nv_rd32(priv, 0x0010a018) & nv_rd32(priv, 0x0010a01c);
+
+ intr = nv_rd32(priv, 0x0010a008) & mask;
+
+ nv_debug(priv, "received falcon interrupt: 0x%08x\n", intr);
+ gk20a_pmu_enable_irq(priv, pmc, false);
+
+ if (!intr || priv->pmu_state == PMU_STATE_OFF) {
+ nv_wr32(priv, 0x0010a004, intr);
+ nv_error(priv, "pmu state off\n");
+ gk20a_pmu_enable_irq(priv,...
2015 Mar 11
0
[PATCH] pmu/gk20a: PMU boot support.
...m_pmu(pmu));
> + unsigned long end_jiffies = jiffies + msecs_to_jiffies(timeout);
> + unsigned long delay = GK20A_IDLE_CHECK_DEFAULT;
> +
> + do {
> + if (*var == val)
> + return 0;
> +
> + if (nv_rd32(ppmu, 0x0010a008))
> + gk20a_pmu_isr(ppmu);
> +
> + usleep_range(delay, delay * 2);
> + delay = min_t(u32, delay << 1, GK20A_IDLE_CHECK_MAX);
> + } while (time_before(jiffies, end_jiffies));
> +
> + return -ETIMEDOUT;
> +}
&...
2015 Mar 11
3
[PATCH] pmu/gk20a: PMU boot support.
...u32 timeout,
+ u32 *var, u32 val)
+{
+ struct nvkm_pmu *ppmu = (void *)nvkm_pmu((void *)
+ impl_from_pmu(pmu));
+ unsigned long end_jiffies = jiffies + msecs_to_jiffies(timeout);
+ unsigned long delay = GK20A_IDLE_CHECK_DEFAULT;
+
+ do {
+ if (*var == val)
+ return 0;
+
+ if (nv_rd32(ppmu, 0x0010a008))
+ gk20a_pmu_isr(ppmu);
+
+ usleep_range(delay, delay * 2);
+ delay = min_t(u32, delay << 1, GK20A_IDLE_CHECK_MAX);
+ } while (time_before(jiffies, end_jiffies));
+
+ return -ETIMEDOUT;
+}
+
+void pmu_dump_falcon_stats(struct pmu_desc *pmu)
+{
+ struct nvkm_pmu *ppmu = (void *)nvkm_pmu((...
2015 Mar 12
2
[PATCH] pmu/gk20a: PMU boot support.
...m_pmu(pmu));
> + unsigned long end_jiffies = jiffies + msecs_to_jiffies(timeout);
> + unsigned long delay = GK20A_IDLE_CHECK_DEFAULT;
> +
> + do {
> + if (*var == val)
> + return 0;
> +
> + if (nv_rd32(ppmu, 0x0010a008))
> + gk20a_pmu_isr(ppmu);
> +
> + usleep_range(delay, delay * 2);
> + delay = min_t(u32, delay << 1, GK20A_IDLE_CHECK_MAX);
> + } while (time_before(jiffies, end_jiffies));
> +
> + return -ETIMEDOUT;
> +}
&...
2015 Apr 08
3
[PATCH V2] pmu/gk20a: PMU boot support.
...*subdev)
+{
+ struct nvkm_pmu *ppmu = nvkm_pmu(subdev);
+ struct gk20a_pmu_priv *pmu = to_gk20a_priv(ppmu);
+ struct nvkm_mc *pmc = nvkm_mc(ppmu);
+ u32 intr, mask;
+ if (!pmu->isr_enabled)
+ return;
+
+ mask = nv_rd32(ppmu, 0x0010a018) & nv_rd32(ppmu, 0x0010a01c);
+
+ intr = nv_rd32(ppmu, 0x0010a008) & mask;
+
+ nv_error(ppmu, "received falcon interrupt: 0x%08x", intr);
+ pmu_enable_irq(ppmu, pmc, false);
+ if (!intr || pmu->pmu_state == PMU_STATE_OFF) {
+ nv_wr32(ppmu, 0x0010a004, intr);
+ nv_error(ppmu, "pmu state off\n");
+ pmu_enable_irq(ppmu, pmc, true);
+ g...
2015 Apr 30
2
[PATCH v4] pmu/gk20a: PMU boot support
...truct nvkm_mc *pmc = nvkm_mc(priv);
>> + u32 intr, mask;
>> +
>> + if (!priv->isr_enabled)
>> + return;
>> +
>> + mask = nv_rd32(priv, 0x0010a018) & nv_rd32(priv, 0x0010a01c);
>> +
>> + intr = nv_rd32(priv, 0x0010a008) & mask;
>> +
>> + nv_debug(priv, "received falcon interrupt: 0x%08x\n", intr);
>> + gk20a_pmu_enable_irq(priv, pmc, false);
>> +
>> + if (!intr || priv->pmu_state == PMU_STATE_OFF) {
>> + nv_wr32(priv, 0x0010a004,...