Displaying 20 results from an estimated 54 matches for "0x000000f0".
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2009 Nov 05
6
Some cosmetic NV10TCL method changes.
The attached patch does the cosmetic renouveau.xml changes I
proposed. I'm about to reply myself with some other patches to update
libdrm and then fix the API break up.
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2009 Dec 26
3
[PATCH 1/3] nouveau: Drop some annoying _DX_ (direct x?) object name prefixes.
...EXTURED_TRIANGLE_SPECULAR__SIZE 0x00000040
-#define NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_I0_SHIFT 0
-#define NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_I0_MASK 0x0000000f
-#define NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_I1_SHIFT 4
-#define NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_I1_MASK 0x000000f0
-#define NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_I2_SHIFT 8
-#define NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_I2_MASK 0x00000f00
-#define NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_I3_SHIFT 12
-#define NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_I3_MASK 0x0000f000
-#define NV03_DX3_TEXTURED_TRIAN...
2010 Jun 04
1
PFIFO_DMA_PUSHER + Xen + NV30 + questions.
...=0x80011639
[ 13.271499] [drm] nouveau 0000:01:00.0: nouveau_gpuobj_ref_add:457 - ch0 h=0x8000000e gpuobj=ffff88000219ac00
[ 13.271499] [drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:75 - ch0 handle=0x8000000e
[ 13.271499] [drm] nouveau 0000:01:00.0: nouveau_ramht_hash_handle:86 - hash=0x000000f0
[ 13.271499] [drm] nouveau 0000:01:00.0: nouveau_ramht_insert:141 - insert ch0 0x000000f0: h=0x8000000e, c=0x80000004
[ 13.271499] [drm] nouveau 0000:01:00.0: nouveau_gpuobj_dma_new:679 - ch0 class=0x003d offset=0x40000 size=0x20
[ 13.271499] [drm] nouveau 0000:01:00.0: nouveau_gpuobj_dma_new...
2013 Feb 21
2
[PATCH] xen: consolidate implementations of LOG() macro
...@@ -18,13 +19,6 @@
#define OFFSET(_sym, _str, _mem) \
DEFINE(_sym, offsetof(_str, _mem));
-/* base-2 logarithm */
-#define __L2(_x) (((_x) & 0x00000002) ? 1 : 0)
-#define __L4(_x) (((_x) & 0x0000000c) ? ( 2 + __L2( (_x)>> 2)) : __L2( _x))
-#define __L8(_x) (((_x) & 0x000000f0) ? ( 4 + __L4( (_x)>> 4)) : __L4( _x))
-#define __L16(_x) (((_x) & 0x0000ff00) ? ( 8 + __L8( (_x)>> 8)) : __L8( _x))
-#define LOG_2(_x) (((_x) & 0xffff0000) ? (16 + __L16((_x)>>16)) : __L16(_x))
-
void __dummy__(void)
{
OFFSET(UREGS_sp, struct cpu_user_regs, sp);
dif...
2015 Oct 14
1
Bug#801768: blktap-dkms: module FTBFS for Linux 4.2: error: too many arguments to function 'mempool_resize'
...'
#define __RD2(_x) (((_x) & 0x00000002) ? 0x2 : ((_x) & 0x1))
^
/usr/src/linux-headers-4.2.0-1-common/include/xen/interface/io/ring.h:17:66: note: in expansion of macro '__RD4'
#define __RD8(_x) (((_x) & 0x000000f0) ? __RD4((_x)>>4)<<4 : __RD4(_x))
^
/usr/src/linux-headers-4.2.0-1-common/include/xen/interface/io/ring.h:18:66: note: in expansion of macro '__RD8'
#define __RD16(_x) (((_x) & 0x0000ff00) ? __RD8((_x)>...
2017 Sep 09
5
Bug#874751: blktap-dkms: module FTBFS for Linux 4.12
...39;
#define __RD2(_x) (((_x) & 0x00000002) ? 0x2 : ((_x) & 0x1))
^~
/usr/src/linux-headers-4.12.0-1-common/include/xen/interface/io/ring.h:17:66: note: in expansion of macro '__RD4'
#define __RD8(_x) (((_x) & 0x000000f0) ? __RD4((_x)>>4)<<4 : __RD4(_x))
^~~~~
/usr/src/linux-headers-4.12.0-1-common/include/xen/interface/io/ring.h:18:66: note: in expansion of macro '__RD8'
#define __RD16(_x) (((_x) & 0x0000ff00) ? __RD8((_x...
2014 Oct 05
1
Bug#764132: fails to compile with linux-image-3.16-2-amd64
...macro ?__RD2?
#define __RD2(_x) (((_x) & 0x00000002) ? 0x2 : ((_x) & 0x1))
^
/usr/src/linux-headers-3.16-2-common/include/xen/interface/io/ring.h:17:66: note: in expansion of macro ?__RD4?
#define __RD8(_x) (((_x) & 0x000000f0) ? __RD4((_x)>>4)<<4 : __RD4(_x))
^
/usr/src/linux-headers-3.16-2-common/include/xen/interface/io/ring.h:18:66: note: in expansion of macro ?__RD8?
#define __RD16(_x) (((_x) & 0x0000ff00) ? __RD8((_x)>>8)<...
2007 Jun 22
0
[PATCH] Commented out all macros that are not used - it still compiles.
...216_BYTES 0x000000D0
-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_224_BYTES 0x000000D8
-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_232_BYTES 0x000000E0
-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_240_BYTES 0x000000E8
-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_248_BYTES 0x000000F0
-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_256_BYTES 0x000000F8
-# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE 0x0000E000
-# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_32_BYTES 0x00000000
-# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_64_BYTES 0x00002000
-# define NV...
2010 Jan 04
1
NV_PFIFO_INTR_DMA_PUSHER
...nouveau Ch0/0x000000d4: 0x80000005
[drm] nouveau Ch0/0x000000d8: 0x80000004
[drm] nouveau Ch0/0x000000dc: 0x0020030c
[drm] nouveau Ch0/0x000000e0: 0x00004000
[drm] nouveau Ch0/0x000000e4: 0x0080b000
[drm] nouveau Ch0/0x000000e8: 0x00001000
[drm] nouveau Ch0/0x000000ec: 0x00001000
[drm] nouveau Ch0/0x000000f0: 0x00001000
[drm] nouveau Ch0/0x000000f4: 0x00000004
[drm] nouveau Ch0/0x000000f8: 0x00000101
[drm] nouveau Ch0/0x000000fc: 0x00000000
[drm] nouveau Ch0/0x00000100: 0x00040100
[drm] nouveau Ch0/0x00000104: 0x00000000
EMIT: Ch0 -> 2
[drm] nouveau Ch0/0x00000108: 0x00040050
[drm] nouveau Ch0/0x000...
2006 May 03
1
demo() output looks garbled in default pager (less and most)
...E202020 20202020 20202020 rsion
0x000000B0: 20202020 5573696E 67207265 63757273 Using recurs
0x000000C0: 696F6E20 666F7220 61646170 74697665 ion for adaptive
0x000000D0: 20696E74 65677261 74696F6E 0A73636F integration.sco
0x000000E0: 70696E67 20202020 20202020 20202020 ping
0x000000F0: 20202020 20416E20 696C6C75 73747261 An illustra
0x00000100: 74696F6E 206F6620 6C657869 63616C20 tion of lexical
0x00000110: 73636F70 696E672E 0A0A4465 6D6F7320 scoping...Demos
0x00000120: 696E2070 61636B61 676520E2 80986772 in package ?..gr
0x00000130: 61706869 6373E280 993A0A...
2014 Dec 31
0
[PATCH 2/2] nvc0: regenerate rnndb headers
...fine NVC0_3D_TESS_MODE_PRIM__SHIFT 0
-#define NVC0_3D_TESS_MODE_PRIM_ISOLINES 0x00000000
+#define NVC0_3D_TESS_MODE_PRIM_ISOLINES 0x00000000
#define NVC0_3D_TESS_MODE_PRIM_TRIANGLES 0x00000001
#define NVC0_3D_TESS_MODE_PRIM_QUADS 0x00000002
-#define NVC0_3D_TESS_MODE_SPACING__MASK 0x000000f0
+#define NVC0_3D_TESS_MODE_SPACING__MASK 0x00000030
#define NVC0_3D_TESS_MODE_SPACING__SHIFT 4
-#define NVC0_3D_TESS_MODE_SPACING_EQUAL 0x00000000
+#define NVC0_3D_TESS_MODE_SPACING_EQUAL 0x00000000
#define NVC0_3D_TESS_MODE_SPACING_FRACTIONAL_ODD 0x00000010
#define NVC0_3D_TESS_MODE_S...
2016 Oct 16
10
[PATCH 1/5] hwdefs: update nvc0_3d, add gm107_texture for new TIC format
..._TIC2_7 0x0000001c
+#define GM107_TIC2_7_COLOR_KEY_VALUE__MASK 0xffffffff
+#define GM107_TIC2_7_COLOR_KEY_VALUE__SHIFT 0
+#define GM107_TIC2_7_RES_VIEW_MIN_MIP_LEVEL__MASK 0x0000000f
+#define GM107_TIC2_7_RES_VIEW_MIN_MIP_LEVEL__SHIFT 0
+#define GM107_TIC2_7_RES_VIEW_MAX_MIP_LEVEL__MASK 0x000000f0
+#define GM107_TIC2_7_RES_VIEW_MAX_MIP_LEVEL__SHIFT 4
+#define GM107_TIC2_7_MULTI_SAMPLE_COUNT__MASK 0x00000f00
+#define GM107_TIC2_7_MULTI_SAMPLE_COUNT__SHIFT 8
+#define GM107_TIC2_7_MULTI_SAMPLE_COUNT_1X1 0x00000000
+#define GM107_TIC2_7_MULTI_SAMPLE_COUNT_2X1 0x00000100
+#define GM107_T...
2014 Dec 31
2
[PATCH 1/2] nv50: regenerate rnndb headers
...0x00000208 + 0x20*(i0))
-#define NV50_3D_RT_TILE_MODE(i0) (0x0000020c + 0x20*(i0))
+#define NV50_3D_RT_TILE_MODE(i0) (0x0000020c + 0x20*(i0))
#define NV50_3D_RT_TILE_MODE_X__MASK 0x0000000f
#define NV50_3D_RT_TILE_MODE_X__SHIFT 0
#define NV50_3D_RT_TILE_MODE_Y__MASK 0x000000f0
@@ -129,11 +129,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define NV50_3D_VTX_ATTR_1F(i0) (0x00000300 + 0x4*(i0))
#define NV50_3D_VTX_ATTR_1F__ESIZE 0x00000004
-#define NV50_3D_VTX_ATTR_1F__LEN 0x00000010
+#define NV50_3D_VTX_ATTR_1F__LEN 0x000000...
2014 Oct 06
21
[Bug 84706] New: [NV94] HDMI Connected, but TV reports "no signal"
https://bugs.freedesktop.org/show_bug.cgi?id=84706
Bug ID: 84706
Summary: [NV94] HDMI Connected, but TV reports "no signal"
Product: xorg
Version: unspecified
Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NEW
Severity: normal
Priority: medium
Component: Driver/nouveau
2012 Sep 20
2
Xorg nvidia-driver GT 650M cause system reboot on my MacBook Retina 9.1RC1
...Sep 20 15:40:31 rmbp kernel: cpu0 BSP:
Sep 20 15:40:31 rmbp kernel: ID: 0x00000000 VER: 0x01060015 LDR: 0x00000000 DFR: 0xffffffff
Sep 20 15:40:31 rmbp kernel: lint0: 0x00010700 lint1: 0x00000400 TPR: 0x00000000 SVR: 0x000001ff
Sep 20 15:40:31 rmbp kernel: timer: 0x000100ef therm: 0x00010000 err: 0x000000f0 pmc: 0x00010400
Sep 20 15:40:31 rmbp kernel: cmci: 0x000000f2
Sep 20 15:40:31 rmbp kernel: Cuse4BSD v0.1.26 @ /dev/cuse
Sep 20 15:40:31 rmbp kernel: wlan: <802.11 Link Layer>
Sep 20 15:40:31 rmbp kernel: snd_unit_init() u=0x00ff8000 [512] d=0x00007c00 [32] c=0x000003ff [1024]
Sep 20 15:40:31...
2012 Aug 02
1
Problem detecting Sil3124 SATA controllers off of Sandy Bridge northbridge-connected PCIe slots
...apic: LINT1 trigger: edge
lapic: LINT1 polarity: high
ioapic0 <Version 2.0> irqs 0-23 on motherboard
cpu0 BSP:
ID: 0x00000000 VER: 0x01060015 LDR: 0x00000000 DFR: 0xffffffff
lint0: 0x00010700 lint1: 0x00000400 TPR: 0x00000000 SVR: 0x000001ff
timer: 0x000100ef therm: 0x00010000 err: 0x000000f0 pmc: 0x00010400
cmci: 0x000000f2
snd_unit_init() u=0x00ff8000 [512] d=0x00007c00 [32] c=0x000003ff [1024]
feeder_register: snd_unit=-1 snd_maxautovchans=16 latency=5 feeder_rate_min=1 feeder_rate_max=2016000 feeder_rate_round=25
wlan: <802.11 Link Layer>
random: <entropy source, Softwar...
2016 Oct 27
11
[PATCH v2 0/7] Add Maxwell support
I believe I've addressed all the feedback from the first time around, and
also made fixes necessary for GM20x based on testing results. I believe
now it should actually work for all GM10x and GM20x. Further, GP10x should
be very easy to add, but without someone to actually test I didn't want to
claim support for it.
Ilia Mirkin (7):
exa: add GM10x acceleration support
hwdefs: update
2012 Oct 02
1
ahcich reset -> cannot mount zfs root in 9.1-PRE
...tpin 9 trigger: level
ioapic0: intpin 9 polarity: low
ioapic0 <Version 2.1> irqs 0-23 on motherboard
cpu0 BSP:
ID: 0x00000000 VER: 0x80050010 LDR: 0x00000000 DFR: 0xffffffff
lint0: 0x00010700 lint1: 0x00000400 TPR: 0x00000000 SVR: 0x000001ff
timer: 0x000100ef therm: 0x00010000 err: 0x000000f0 pmc: 0x00010400
wlan: <802.11 Link Layer>
snd_unit_init() u=0x00ff8000 [512] d=0x00007c00 [32] c=0x000003ff [1024]
feeder_register: snd_unit=-1 snd_maxautovchans=16 latency=5 feeder_rate_min=1 feeder_rate_max=2016000 feeder_rate_round=25
kbd: new array size 4
kbd1 at kbdmux0
mem: <memory&g...
2016 Feb 15
24
[PATCH 01/23] nv50: import updated g80_defs.xml.h from rnndb
...a
+#define G80_SURFACE_FORMAT_RG8_SNORM 0x000000eb
+#define G80_SURFACE_FORMAT_RG8_SINT 0x000000ec
+#define G80_SURFACE_FORMAT_RG8_UINT 0x000000ed
+#define G80_SURFACE_FORMAT_R16_UNORM 0x000000ee
+#define G80_SURFACE_FORMAT_R16_SNORM 0x000000ef
+#define G80_SURFACE_FORMAT_R16_SINT 0x000000f0
+#define G80_SURFACE_FORMAT_R16_UINT 0x000000f1
+#define G80_SURFACE_FORMAT_R16_FLOAT 0x000000f2
+#define G80_SURFACE_FORMAT_R8_UNORM 0x000000f3
+#define G80_SURFACE_FORMAT_R8_SNORM 0x000000f4
+#define G80_SURFACE_FORMAT_R8_SINT 0x000000f5
+#define G80_SURFACE_FORMAT_R8_UINT 0x000...
2010 Feb 25
3
[PATCH 1/3] drm/nv50: Implement ctxprog/state generation.
...def(ctx, offset + 0x2bc, 0x00000070);
+ gr_def(ctx, offset + 0x2c0, 0x00000080);
+ gr_def(ctx, offset + 0x2cc, 0x00000001);
+ gr_def(ctx, offset + 0x2d0, 0x00000070);
+ gr_def(ctx, offset + 0x2d4, 0x00000080);
+ } else {
+ gr_def(ctx, offset + 0x2b8, 0x00000001);
+ gr_def(ctx, offset + 0x2bc, 0x000000f0);
+ gr_def(ctx, offset + 0x2c0, 0x000000ff);
+ gr_def(ctx, offset + 0x2cc, 0x00000001);
+ gr_def(ctx, offset + 0x2d0, 0x000000f0);
+ gr_def(ctx, offset + 0x2d4, 0x000000ff);
+ gr_def(ctx, offset + 0x2dc, 0x00000009);
+ offset += 4;
+ }
+ gr_def(ctx, offset + 0x2e4, 0x00000001);
+ gr_def(ctx,...