Displaying 4 results from an estimated 4 matches for "0f0h".
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2012 Feb 14
0
[LLVMdev] Strange behaviour with x86-64 windows, bad call instruction address
...FFFC5121A  je          000007FFFFC511C3
000007FFFFC51220  mov         qword ptr [rbp-68h],rdi
000007FFFFC51224  mov         eax,10h
000007FFFFC51229  call        0000080077B3F1D0
000007FFFFC5122E  sub         rsp,rax
000007FFFFC51231  mov         rdx,rsp
000007FFFFC51234  mov         qword ptr [rbp-0F0h],rdx
000007FFFFC5123B  sub         rsp,20h
The call instruction at 000007FFFFC51229  is the one that jumps into invalid memory at 80077B3F1D0.  I'm not sure why this particular EXE causes llvm to use such large address values, but it looks like there might be some 32 bit vs 64 bit address calc...
2013 Jul 19
0
[LLVMdev] llvm.x86.sse2.sqrt.pd not using sqrtpd, calling a function that modifies ECX
...xmm0,xmm0 
002E010C  movapd      xmmword ptr [esp+0C0h],xmm0 
002E0115  xorpd       xmm1,xmm1 
002E0119  xorpd       xmm7,xmm7 
002E011D  movapd      xmmword ptr [esp+0A0h],xmm1 
002E0126  movapd      xmmword ptr [esp+0B0h],xmm7 
002E012F  movapd      xmm3,xmm1 
002E0133  movlpd      qword ptr [esp+0F0h],xmm3 
002E013C  movhpd      qword ptr [esp+0E0h],xmm3 
002E0145  movlpd      qword ptr [esp+100h],xmm7 
002E014E  pshufd      xmm0,xmm7,44h 
002E0153  movdqa      xmm5,xmm0 
002E0157  xorpd       xmm4,xmm4 
002E015B  mulpd       xmm5,xmm4 
002E015F  pshufd      xmm2,xmm3,44h 
002E0164  movdqa...
2012 Feb 21
0
[LLVMdev] Strange behaviour with x86-64 windows, bad call instruction address
...FFFC5121A  je          000007FFFFC511C3
000007FFFFC51220  mov         qword ptr [rbp-68h],rdi
000007FFFFC51224  mov         eax,10h
000007FFFFC51229  call        0000080077B3F1D0
000007FFFFC5122E  sub         rsp,rax
000007FFFFC51231  mov         rdx,rsp
000007FFFFC51234  mov         qword ptr [rbp-0F0h],rdx
000007FFFFC5123B  sub         rsp,20h
The call instruction at 000007FFFFC51229  is the one that jumps into invalid memory at 80077B3F1D0.  I'm not sure why this particular EXE causes llvm to use such large address values, but it looks like there might be some 32 bit vs 64 bit address calc...
2013 Jul 19
4
[LLVMdev] SIMD instructions and memory alignment on X86
Hmm, I'm not able to get those .ll files to compile if I disable SSE and I
end up with SSE instructions(including sqrtpd) if I don't disable it.
On Thu, Jul 18, 2013 at 10:53 PM, Peter Newman <peter at uformia.com> wrote:
>  Is there something specifically required to enable SSE? If it's not
> detected as available (based from the target triple?) then I don't think