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On Jan 10, 2013, at 9:54 PM, Kenneth Waters <kwwaters at gmail.com> wrote: > I have a pattern where I load the 16 bit portion of the register with 0, and then copy in the 8 bit portion. > > def : Pat<(i16 (zextloadi8 addr:$src)), > (INSERT_SUBREG (MOV16id 0), (MOV8md addr:$src), sub_byte)>; > > which produces working but odd assembly, > >

...scheduler into putting these in the right order? Perhaps by adding a scheduling dependency between the move and the load? Thank you, -- Kenneth Waters -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130111/0e7dff2f/attachment.html>

llvm-dev, I'm trying to get a better understanding of sub-registers. I'm seeing the code generator make an odd decision that I was hoping someone could point me in the right direction of explaining. The architecture is 68000, which has 8, 16, and 32 bit views of all of it's data registers. In order to zero extend you can load a big view with zero, and then copy into the small view.