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...Type-legalizer discover this information when lowering the truncate? Is the problem that this knowledge is not know in the DAG, only in the IR? Robert -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130911/0e2f65e1/attachment.html> -------------- next part -------------- A non-text attachment was scrubbed... Name: arm-strcspn.s Type: application/octet-stream Size: 1710 bytes Desc: arm-strcspn.s URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130911/0e2f65e1/attachment.obj>

On Sep 10, 2013, at 8:59 AM, Robert Lytton <robert at xmos.com> wrote: > Hi, > > A bit more information. > I believe my problem lies with the fact that the load is left as 'anyext from i8'. > On the XCore target we know this will become an 8bit zext load - as there is no 8bit sign extended load! > If BB#1 were to force the load to a "zext from i8" would