Displaying 19 results from an estimated 19 matches for "0ch".
Did you mean:
0c
2005 Mar 11
0
[LLVMdev] FP Intrinsics
...160456 fstp st(0)
17160458 fnstsw ax
1716045A sahf
1716045B fldz
1716045D fchs
1716045F fld qword ptr [esp+14h]
17160463 fucomip st,st(1)
17160465 fstp st(0)
17160467 jbe 17160498
1716046D mov eax,76E4F60h
17160472 mov dword ptr [esp+0Ch],eax
17160476 fld qword ptr [esp+14h]
1716047A fstp dword ptr [esp+8]
1716047E mov eax,15900060h
17160483 mov dword ptr [esp+4],eax
17160487 mov eax,161D6240h
1716048C mov dword ptr [esp],eax
1716048F call HueVMShaderCommands_LLVMShader1D...
2011 Nov 02
5
[LLVMdev] About JIT by LLVM 2.9 or later
...[eax]
013C143D mov dword ptr [ebp-150h],edx
013C1443 mov ecx,dword ptr [eax+4]
013C1446 mov dword ptr [ebp-14Ch],ecx
013C144C mov edx,dword ptr [eax+8]
013C144F mov dword ptr [ebp-148h],edx
013C1455 mov eax,dword ptr [eax+0Ch]
013C1458 mov dword ptr [ebp-144h],eax
013C145E mov ecx,dword ptr [ebp-150h]
// Copy secondary temporary to variable 'b'
013C1464 mov dword ptr [ebp-60h],ecx
013C1467 mov edx,dword ptr [ebp-14Ch]
013C146D mov dword ptr [e...
2005 Mar 11
5
[LLVMdev] FP Intrinsics
Hello,
I am trying to make the FP intrinsics (abs, sin, cos, sqrt) I've added
work with the X86ISelPattern, but I'm having some difficulties
understanding what needs to be done. I assume I have to add new
nodetypes for the FP instructions to SelectionDAGNodes.h, and make nodes
for these in SelectionDAGLowering::visitCall when I find the intrinsic...
The part I don't quite
2012 Mar 31
1
[LLVMdev] llvm.exp.f32 didn't work
...g ASM:
00280072 movups xmm0,xmmword ptr [esp+8]
00280077 movss dword ptr [esp],xmm0
0028007C call 00000000
00280081 pop eax
As you seen, line 0028007C will call CRT exp I think, but it calls NULL
pointer.
But sqrt is right.
005000D1 movss xmm0,dword ptr [esp+0Ch]
005000D7 movss dword ptr [esp],xmm0
005000DC call 00490018
005000E1 mov eax,dword ptr [esp+8]
Could you give me some help ? Thanks !
--
Ye Wu
CELL: +86 159 9957 0103
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llv...
2013 Jul 19
0
[LLVMdev] llvm.x86.sse2.sqrt.pd not using sqrtpd, calling a function that modifies ECX
...movapd xmm4,xmmword ptr [esp+70h]
002E0176 subpd xmm4,xmm1
002E017A pshufd xmm3,xmm3,0EEh
002E017F subpd xmm4,xmm3
002E0183 subpd xmm4,xmm5
002E0187 fld qword ptr [esp+0F0h]
002E018E call 76719BA1 CALL
002E0193 imul ebx,eax,0Ch
002E0196 lea esi,[ebx+3]
002E0199 shl esi,4
002E019C movapd xmm6,xmmword ptr [esi+2C0030h]
002E01A4 mulpd xmm6,xmm4
002E01A8 mulpd xmm3,xmm7
002E01AC movapd xmm7,xmmword ptr [esp+60h]
002E01B2 subpd xmm7,xmm2
002E01B6 subpd xmm7,xmm3...
2011 Oct 26
2
[LLVMdev] Lowering to MMX
...store x86_mmx %7, x86_mmx* %8, align 1
ret void
}
declare x86_mmx @llvm.x86.mmx.punpcklbw(x86_mmx, x86_mmx) nounwind readnone
Which gives me the following assembly code:
push ebp
mov ebp,esp
and esp,0FFFFFFF0h
sub esp,20h
mov eax,dword ptr [ebp+0Ch]
movd xmm0,dword ptr [eax]
movapd xmmword ptr [esp],xmm0
movq mm0,mmword ptr [esp]
punpcklbw mm0,mm0
mov eax,dword ptr [ebp+8]
movq mmword ptr [eax],mm0
emms
mov esp,ebp
pop ebp
ret
The inner portion could look like this inste...
2011 Oct 26
0
[LLVMdev] Lowering to MMX
...; ret void
> }
> declare x86_mmx @llvm.x86.mmx.punpcklbw(x86_mmx, x86_mmx) nounwind readnone
>
> Which gives me the following assembly code:
>
> push ebp
> mov ebp,esp
> and esp,0FFFFFFF0h
> sub esp,20h
> mov eax,dword ptr [ebp+0Ch]
> movd xmm0,dword ptr [eax]
> movapd xmmword ptr [esp],xmm0
> movq mm0,mmword ptr [esp]
> punpcklbw mm0,mm0
> mov eax,dword ptr [ebp+8]
> movq mmword ptr [eax],mm0
> emms
> mov esp,ebp
> pop ebp
> ret
>
> The...
2001 Dec 11
0
VirtualProtect and app crash: what's your interpretation?
...test eax, eax
00760DD2 jz loc_760EB4
00760DD8
00760DD8 loc_760DD8: ; CODE XREF:
sub_760D4A+164^Yj
00760DD8 mov ecx, ds:dword_75D728
00760DDE lea edi, [ecx+eax]
00760DE1 mov eax, [esi+0Ch]
00760DE4 add eax, ecx
00760DE6 push eax
00760DE7 mov [ebp-10h], eax
00760DEA call ds:LoadLibraryA
00760DF0 mov [ebp-0Ch], eax
00760DF3 test eax, eax
00760DF5 jnz...
2012 Jul 05
0
[LLVMdev] clang optimizer does not remove unused/uneeded variables(and accesses) from global scope
...)random;
dword_t result = 3*(byte+dword);
return result;
}
-------
compiled with "clang -O3 test.c"
produces this code for the main
.text:004012E0 sub_4012E0 proc near ; CODE XREF:
sub_401020+91
.text:004012E0
.text:004012E0 arg_4 = dword ptr 0Ch
.text:004012E0
.text:004012E0 push ebp
.text:004012E1 mov ebp, esp
.text:004012E3 call sub_4014C0
.text:004012E8 mov eax, [ebp+arg_4] ; dword_t random
= (dword_t)argv;
.text:004012EB mov byte_402000,...
2009 Mar 22
1
[PATCH] [memdisk] Additional comments in memdisk.inc and postprocess.pl
...FLAGS
dw Invalid ; 07h - FORMAT DRIVE AT TRACK
dw GetParms ; 08h - GET PARAMETERS
- dw InitWithParms ; 09h - INITIALIZE CONTROLLER
WITH DRIVE PARAMETERS
+ dw InitWithParms ; 09h - INITIALIZE CONTROLLER
WITH
+ ; DRIVE PARAMETERS
dw Invalid ; 0Ah
dw Invalid ; 0Bh
dw Seek ; 0Ch - SEEK TO CYLINDER
diff --git a/memdisk/postprocess.pl b/memdisk/postprocess.pl
index f8cba96..fcda478 100755
--- a/memdisk/postprocess.pl
+++ b/memdisk/postprocess.pl
@@ -12,8 +12,10 @@
##
-----------------------------------------------------------------------
#
-# Postprocess the memdisk bina...
2013 Jul 19
4
[LLVMdev] SIMD instructions and memory alignment on X86
Hmm, I'm not able to get those .ll files to compile if I disable SSE and I
end up with SSE instructions(including sqrtpd) if I don't disable it.
On Thu, Jul 18, 2013 at 10:53 PM, Peter Newman <peter at uformia.com> wrote:
> Is there something specifically required to enable SSE? If it's not
> detected as available (based from the target triple?) then I don't think
2015 Feb 13
2
[LLVMdev] trunk's optimizer generates slower code than 3.5
...ptr -78h
var_74 = dword ptr -74h
var_70 = dword ptr -70h
var_6C = dword ptr -6Ch
var_68 = dword ptr -68h
var_64 = dword ptr -64h
var_60 = dword ptr -60h
var_5C = dword ptr -5Ch
argc = dword ptr 8
argv = dword ptr 0Ch
envp = dword ptr 10h
push ebp
mov ebp, esp
and esp, 0FFFFFF80h
push esi
push edi
push ebx
sub esp, 74h
push 3
call...
2015 Feb 14
2
[LLVMdev] trunk's optimizer generates slower code than 3.5
...rd ptr -70h
>> var_6C = dword ptr -6Ch
>> var_68 = dword ptr -68h
>> var_64 = dword ptr -64h
>> var_60 = dword ptr -60h
>> var_5C = dword ptr -5Ch
>> argc = dword ptr 8
>> argv = dword ptr 0Ch
>> envp = dword ptr 10h
>>
>> push ebp
>> mov ebp, esp
>> and esp, 0FFFFFF80h
>> push esi
>> push edi
>> push ebx
>>...
2007 Sep 28
2
[LLVMdev] Vector troubles
...i32 3
; <float*> [#uses=1]
store float %elemToDemote16, float* %elemPtr17
ret void
}
Assembler (intel format):
15c00010 83ec2c sub esp,2Ch
15c00013 8b442434 mov eax,dword ptr [esp+34h]
15c00017 f30f10400c movss xmm0,dword ptr [eax+0Ch]
15c0001c f30f104804 movss xmm1,dword ptr [eax+4]
15c00021 0f14c8 unpcklps xmm1,xmm0
15c00024 f30f104008 movss xmm0,dword ptr [eax+8]
15c00029 f30f1010 movss xmm2,dword ptr [eax]
15c0002d 0f14d0 unpcklps xmm2,xmm0
15c00030 0f14d1 unpcklps xmm2...
2015 Feb 14
2
[LLVMdev] trunk's optimizer generates slower code than 3.5
...-6Ch
>>>> var_68 = dword ptr -68h
>>>> var_64 = dword ptr -64h
>>>> var_60 = dword ptr -60h
>>>> var_5C = dword ptr -5Ch
>>>> argc = dword ptr 8
>>>> argv = dword ptr 0Ch
>>>> envp = dword ptr 10h
>>>>
>>>> push ebp
>>>> mov ebp, esp
>>>> and esp, 0FFFFFF80h
>>>> push esi
>>>> pu...
2011 Oct 25
0
[LLVMdev] Lowering to MMX
On Oct 20, 2011, at 8:42 AM, Nicolas Capens wrote:
> Hi all,
>
> I'm working on a graphics project which uses LLVM for dynamic code
> generation, and I noticed a major performance regression when upgrading
> from LLVM 2.8 to 3.0-rc1 (LLVM 2.9 didn't support Win64 so I skipped it
> entirely).
>
> I found out that the performance regression is due to removing
2012 Mar 07
2
[LLVMdev] Scalar replacement of arrays
...ray entirely. Here's a small piece of C code which
illustrates the problem:
int foo(int x, int y)
{
int r[2];
r[0] = x;
r[1] = y;
r[0] = r[0] + r[1];
return r[0];
}
This gives me the following (x86) assembly code:
sub esp,8
mov eax,dword ptr [esp+0Ch]
mov dword ptr [esp],eax
mov eax,dword ptr [esp+10h]
mov dword ptr [esp+4],eax
add eax,dword ptr [esp]
mov dword ptr [esp],eax
add esp,8
ret
If I replace the array with two individual scalars, I get the following
perfect result instead...
2011 Oct 20
4
[LLVMdev] Lowering to MMX
Hi all,
I'm working on a graphics project which uses LLVM for dynamic code
generation, and I noticed a major performance regression when upgrading
from LLVM 2.8 to 3.0-rc1 (LLVM 2.9 didn't support Win64 so I skipped it
entirely).
I found out that the performance regression is due to removing support
for lowering 64-bit vector operations to MMX, and using SSE2 instead. My
code uses a
2006 Mar 15
0
Samba + Cups -> PPD Options problem - 1 attachment
...ot;5V]R:V9L;W<@57-E0U-!,E\Q+U5S92!3<&ER92!21T(@,BXQ
M.B`B)5-#25!01#H@1$9%(%)'0E]#4T$@0U-!,E\Q(@T**D-87T,R1%]21T)7
M;W)K9FQO=R!5<V5#4T$R7S0O57-E(%-P:7)E(%)'0B`R+C0Z("(E4T-)4%!$
M.B!$1D4@4D="7T-302!#4T$R7S0B#0HJ0UA?0S)$7U)'0E=O<FMF;&]W('-2
M1T(O<U)'0CH@(B530TE04$0Z($1&12!21T)?0U-!('-21T(B#0HJ0UA?0S)$
M7U)'0E=O<FMF;&]W($%D;V)E4D="+T%D;V)E4D=".B`B)5-#25!01#H@1$9%
M(%)'0E]#4T$@061O8F521T(B#0HJ0VQO<V5523H@*D-87T,R1%]21T)7;W)K
M9FQO=PT*#0HJ3W!E;E5)("I#6%]#,D1?4F5N9&5R:6YG1F]R4D="+U)E;F1E
M<FEN9R!);G...