Displaying 6 results from an estimated 6 matches for "0b100111".
2010 Jan 01
2
[LLVMdev] Assembly Printer
...g LLVM 2.6.
First,
if I want to change the name of an instruction, all I need to do is to
modify the XXXInstrInfo.td, right?
Using Sparc as an example, if I wanted to output "mysra" instead of "sra",
in SparcInstrInfo.td, I would write,
defm SRA : F3_12<"mysra", 0b100111, sra>;
Is this correct?
When I run llc with option -march=sparc, after I make the modification, it
still outputs "sra", not "mysra". I looked into SparcGenAsmWriter.inc, and
made sure that string AsmStrs includes "mysra". However, when I run gdb and
do "print...
2010 Jan 03
0
[LLVMdev] Assembly Printer
...> if I want to change the name of an instruction, all I need to do is to modify the XXXInstrInfo.td, right?
> Using Sparc as an example, if I wanted to output "mysra" instead of "sra", in SparcInstrInfo.td, I would write,
>
> defm SRA : F3_12<"mysra", 0b100111, sra>;
>
> Is this correct?
Yes.
> When I run llc with option -march=sparc, after I make the modification, it still outputs "sra", not "mysra". I looked into SparcGenAsmWriter.inc, and made sure that string AsmStrs includes "mysra". However, when I run...
2010 Jan 04
1
[LLVMdev] Assembly Printer
...of an instruction, all I need to do is to
> > modify the XXXInstrInfo.td, right? Using Sparc as an example, if I
> > wanted to output "mysra" instead of "sra", in SparcInstrInfo.td, I would
> > write,
> >
> > defm SRA : F3_12<"mysra", 0b100111, sra>;
> >
> > Is this correct?
>
> Yes.
IMHO, this is a poor way to do this kind of thing. It eventually
leads to confusion where someone things SRA means "sra" and someone
else thinks it meas "mysra." It gets worse as "mysra" acquires
subtly d...
2006 Oct 02
0
[LLVMdev] Instruction descriptions question
...0001, and>;
defm OR : F3_12<"or" , 0b000010, or>;
defm XOR : F3_12<"xor" , 0b000011, xor>;
defm SLL : F3_12<"sll" , 0b100101, shl>;
defm SRL : F3_12<"srl" , 0b100110, srl>;
defm SRA : F3_12<"sra" , 0b100111, sra>;
defm ADD : F3_12<"add" , 0b000000, add>;
defm ADDCC : F3_12<"addcc", 0b010000, addc>;
defm ADDX : F3_12<"addx" , 0b001000, adde>;
defm SUB : F3_12<"sub" , 0b000100, sub>;
defm SUBX : F3_12<"subx" , 0...
2006 Oct 01
2
[LLVMdev] Instruction descriptions question
Hi,
I'm trying to implement a new backend for an embedded CISC processor.
Therefore I thought that it makes sense to take X86 target as a basis,
to save some time.
But when I look into the X86InstrInfo.td, I have a very strong feeling
that it is one of the most complex instruction set descriptions
compared to other targets. I can imagine that this is due to the
complexity of X86's
2006 Oct 02
2
[LLVMdev] Instruction descriptions question
...OR : F3_12<"or" , 0b000010, or>;
> defm XOR : F3_12<"xor" , 0b000011, xor>;
> defm SLL : F3_12<"sll" , 0b100101, shl>;
> defm SRL : F3_12<"srl" , 0b100110, srl>;
> defm SRA : F3_12<"sra" , 0b100111, sra>;
> defm ADD : F3_12<"add" , 0b000000, add>;
> defm ADDCC : F3_12<"addcc", 0b010000, addc>;
> defm ADDX : F3_12<"addx" , 0b001000, adde>;
> defm SUB : F3_12<"sub" , 0b000100, sub>;
> defm SUBX : F3_1...