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0b1001010
2013 Mar 25
0
[LLVMdev] Types in TableGen instruction selection patterns
Jakob Stoklund Olesen wrote:
> I have updated TableGen to support a new format for instruction selection patterns.
>
> Before:
>
> def : Pat<(subc IntRegs:$b, IntRegs:$c), (SUBCCrr IntRegs:$b, IntRegs:$c)>;
>
> After:
>
> def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>;
>
> Since the pattern matching happens on a DAG with type labels, not
2013 Mar 24
5
[LLVMdev] Types in TableGen instruction selection patterns
I have updated TableGen to support a new format for instruction selection patterns.
Before:
def : Pat<(subc IntRegs:$b, IntRegs:$c), (SUBCCrr IntRegs:$b, IntRegs:$c)>;
After:
def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>;
Since the pattern matching happens on a DAG with type labels, not register classes, I think it makes more sense to specify types directly on the input