Displaying 2 results from an estimated 2 matches for "0b010".
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2015 Jan 11
2
[LLVMdev] Backend Tablegen Instruction Definition
...ng the type-I template) that is as follows:
//rdcycle
def RDCYCLE: InstRISCV<4, (outs GR32:$dst), (ins), ([set GC32:$dst])>{
field bits<32> Inst;
bits<5> dst;
let Inst{31-20} = 0b000000000000;
let Inst{19-15} = 0b00000;
let Inst{14-12} = 0b010;
let Inst{11- 7} = dst;
let Inst{6 - 0} = 0b1110011;
}
However, the compilation fails with the follow:
llvm[3]: Building RISCV.td instruction information with tblgen
llvm-tblgen: /home/jleidel/dev/working/jleidel-riscv-llvm/riscv-trunk/utils/TableGen/CodeGenDAGPatterns.cpp:1...
2012 Nov 06
50
chain.c32 (and partiter) updates v2
This is a bit updated set of chain.c32 changes that simplifies a few things
(and in partiter part), fixes few minor issues and adds a few new features.
Details are in the following commits, below is the summary and pull details at
the end.
Shao - any chance to peek over them ? Most of those are relatively simple
changes and well tested, though of course something might have slipped my
attention.