Displaying 3 results from an estimated 3 matches for "0b000011".
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00000011
2006 Oct 02
0
[LLVMdev] Instruction descriptions question
..., $dst"),
[(set IntRegs:$dst, (OpNode IntRegs:$b, simm13:$c))]>;
}
which allows it to use instructions like:
defm AND : F3_12<"and" , 0b000001, and>;
defm OR : F3_12<"or" , 0b000010, or>;
defm XOR : F3_12<"xor" , 0b000011, xor>;
defm SLL : F3_12<"sll" , 0b100101, shl>;
defm SRL : F3_12<"srl" , 0b100110, srl>;
defm SRA : F3_12<"sra" , 0b100111, sra>;
defm ADD : F3_12<"add" , 0b000000, add>;
defm ADDCC : F3_12<"addcc", 0b0...
2006 Oct 01
2
[LLVMdev] Instruction descriptions question
Hi,
I'm trying to implement a new backend for an embedded CISC processor.
Therefore I thought that it makes sense to take X86 target as a basis,
to save some time.
But when I look into the X86InstrInfo.td, I have a very strong feeling
that it is one of the most complex instruction set descriptions
compared to other targets. I can imagine that this is due to the
complexity of X86's
2006 Oct 02
2
[LLVMdev] Instruction descriptions question
...set IntRegs:$dst, (OpNode IntRegs:$b,
simm13:$c))]>;
> }
>
> which allows it to use instructions like:
>
> defm AND : F3_12<"and" , 0b000001, and>;
> defm OR : F3_12<"or" , 0b000010, or>;
> defm XOR : F3_12<"xor" , 0b000011, xor>;
> defm SLL : F3_12<"sll" , 0b100101, shl>;
> defm SRL : F3_12<"srl" , 0b100110, srl>;
> defm SRA : F3_12<"sra" , 0b100111, sra>;
> defm ADD : F3_12<"add" , 0b000000, add>;
> defm ADDCC : F3_12&...