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2015 Jan 11
2
[LLVMdev] Backend Tablegen Instruction Definition
...ycle Rt
I’ve defined a stand-alone instruction definition (as opposed to using the type-I template) that is as follows:
//rdcycle
def RDCYCLE: InstRISCV<4, (outs GR32:$dst), (ins), ([set GC32:$dst])>{
field bits<32> Inst;
bits<5> dst;
let Inst{31-20} = 0b000000000000;
let Inst{19-15} = 0b00000;
let Inst{14-12} = 0b010;
let Inst{11- 7} = dst;
let Inst{6 - 0} = 0b1110011;
}
However, the compilation fails with the follow:
llvm[3]: Building RISCV.td instruction information with tblgen
llvm-tblgen: /home/jleidel/dev/working/jl...