Displaying 3 results from an estimated 3 matches for "0_latency_with_p1".
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0_latency_with_p2
2014 Mar 04
2
[LLVMdev] Question about per-operand machine model
...ed/reserved to avoid any conflict. That's why I believe the new process resource model closely fits what we need, except for the per-resource delay you mentioned.
>>>
>>> This is how our model currently looks like:
>>>
>>> def :ItinRW<[1_LATENCY_WITH_P0, 0_LATENCY_WITH_P1, 0_LATENCY_WITH_P2], [II_ADD]>;
>>> def :ItinRW<[2_LATENCY_WITH_P0, 0_LATENCY_WITH_P1, 0_LATENCY_WITH_P2], [II_MUL]>;
>>>
>>> where n_LATENCY_WITH_p is defined roughly as:
>>>
>>> class n_LATENCY_WITH_p<int latency, ProcResourceKind port>...
2014 Mar 03
2
[LLVMdev] Question about per-operand machine model
...w many cycles these ports are used/reserved to avoid any conflict. That's why I believe the new process resource model closely fits what we need, except for the per-resource delay you mentioned.
>
> This is how our model currently looks like:
>
> def :ItinRW<[1_LATENCY_WITH_P0, 0_LATENCY_WITH_P1, 0_LATENCY_WITH_P2], [II_ADD]>;
> def :ItinRW<[2_LATENCY_WITH_P0, 0_LATENCY_WITH_P1, 0_LATENCY_WITH_P2], [II_MUL]>;
>
> where n_LATENCY_WITH_p is defined roughly as:
>
> class n_LATENCY_WITH_p<int latency, ProcResourceKind port> : SchedWriteRes<[PR_Pp]> {
>...
2014 Feb 28
2
[LLVMdev] Question about per-operand machine model
On Feb 19, 2014, at 1:54 PM, jingu <jingu at codeplay.com> wrote:
> Hi Andy,
>
> I am trying to schedule and packetize instructions for VLIW at post-RA
> stage or final codegen stage, where code transformations are not allowed
> any more, because hardware can not resolve resource conflict. There is a
> simple example as following:
>
> ADD dest_reg1, src_reg1,