Displaying 3 results from an estimated 3 matches for "09selp".
2012 Jul 10
2
[LLVMdev] [NVPTX] CUDA inline PTX asm definitions scoping "{" "}" is broken
...ry:
%a.addr = alloca i32, align 4
%result = alloca i32, align 4
store i32 %a, i32* %a.addr, align 4
%0 = load i32* %a.addr, align 4
%1 = call i32 asm sideeffect "$( \0A\09.reg .pred \09%p1; \0A\09.reg
.pred \09%p2; \0A\09setp.ne.u32 \09%p1, $1, 0; \0A\09vote.any.pred \09%p2,
%p1; \0A\09selp.s32 \09$0, 1, 0, %p2; \0A\09$)", "=r,r"(i32 %0) nounwind,
!srcloc !0
store i32 %1, i32* %result, align 4
%2 = load i32* %result, align 4
ret i32 %2
}
!0 = metadata !{i32 127, i32 132, i32 166, i32 200, i32 242, i32 285, i32
327}
> llc -march=nvptx64 test.ll -o test.ptx
>...
2012 Jul 10
0
[LLVMdev] [NVPTX] CUDA inline PTX asm definitions scoping "{" "}" is broken
...ca i32, align 4
> %result = alloca i32, align 4
> store i32 %a, i32* %a.addr, align 4
> %0 = load i32* %a.addr, align 4
> %1 = call i32 asm sideeffect "$( \0A\09.reg .pred \09%p1; \0A\09.reg .pred \09%p2; \0A\09setp.ne.u32 \09%p1, $1, 0; \0A\09vote.any.pred \09%p2, %p1; \0A\09selp.s32 \09$0, 1, 0, %p2; \0A\09$)", "=r,r"(i32 %0) nounwind, !srcloc !0
> store i32 %1, i32* %result, align 4
> %2 = load i32* %result, align 4
> ret i32 %2
> }
>
> !0 = metadata !{i32 127, i32 132, i32 166, i32 200, i32 242, i32 285, i32 327}
>
> > ll...
2012 Jul 10
1
[LLVMdev] [NVPTX] CUDA inline PTX asm definitions scoping "{" "}" is broken
...ign 4
> %result = alloca i32, align 4
> store i32 %a, i32* %a.addr, align 4
> %0 = load i32* %a.addr, align 4
> %1 = call i32 asm sideeffect "$( \0A\09.reg .pred \09%p1; \0A\09.reg
> .pred \09%p2; \0A\09setp.ne.u32 \09%p1, $1, 0; \0A\09vote.any.pred \09%p2,
> %p1; \0A\09selp.s32 \09$0, 1, 0, %p2; \0A\09$)", "=r,r"(i32 %0) nounwind,
> !srcloc !0
> store i32 %1, i32* %result, align 4
> %2 = load i32* %result, align 4
> ret i32 %2
> }
>
> !0 = metadata !{i32 127, i32 132, i32 166, i32 200, i32 242, i32 285, i32
> 327}
>
>...