Displaying 9 results from an estimated 9 matches for "0886f47e5244".
2014 May 19
1
[PATCH 3/4] drm/nouveau: hook up cache sync functions
...ivers/gpu/drm/nouveau/nouveau_bo.h | 20 ++++++++++++++++++++
> drivers/gpu/drm/nouveau/nouveau_gem.c | 8 +++++++-
> 3 files changed, 59 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
> index b6dc85c614be..0886f47e5244 100644
> --- a/drivers/gpu/drm/nouveau/nouveau_bo.c
> +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
> @@ -407,6 +407,8 @@ nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
> {
> int ret;
>
> + nouveau_bo_sync_for_device(nvbo);
> +
> ret = ttm_bo_validat...
2014 May 19
3
[PATCH 4/4] drm/nouveau: introduce CPU cache flushing macro
...s_addr_t pa = virt_to_phys(va); \
> + __cpuc_flush_dcache_area(va, size); \
> + outer_flush_range(pa, pa + size); \
> +} while (0)
Couldn't this be a static inline function?
> diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
[...]
> index 0886f47e5244..b9c9729c5733 100644
> --- a/drivers/gpu/drm/nouveau/nouveau_bo.c
> +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
> @@ -437,8 +437,10 @@ nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
> mem = &mem[index];
> if (is_iomem)
> iowrite16_native(val, (void __f...
2014 May 19
8
[PATCH 0/4] drm/ttm: nouveau: memory coherency fixes for ARM
This small series introduces TTM helper functions as well as Nouveau hooks that
are needed to ensure buffer coherency on ARM. Most of this series is a
forward-port of some patches Lucas Stach sent last year and that are also
needed for Nouveau GK20A support:
http://lists.freedesktop.org/archives/nouveau/2013-August/014026.html
Another patch takes care of flushing the CPU write-buffer when
2014 May 19
2
[PATCH 4/4] drm/nouveau: introduce CPU cache flushing macro
...ore an explicit cache flush is not
> required.
I was criticizing the wording in the commit message. Perhaps it could be
enhanced with what you just said.
> > > diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
> > [...]
> > > index 0886f47e5244..b9c9729c5733 100644
> > > --- a/drivers/gpu/drm/nouveau/nouveau_bo.c
> > > +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
> > > @@ -437,8 +437,10 @@ nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
> > > mem = &mem[index];
> > > if...
2014 Jun 09
2
[PATCH 4/4] drm/nouveau: introduce CPU cache flushing macro
...>> > + outer_flush_range(pa, pa + size); \
>> > +} while (0)
>>
>> Couldn't this be a static inline function?
>>
>> > diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
>> [...]
>> > index 0886f47e5244..b9c9729c5733 100644
>> > --- a/drivers/gpu/drm/nouveau/nouveau_bo.c
>> > +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
>> > @@ -437,8 +437,10 @@ nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
>> > mem = &mem[index];
>> > if (...
2014 May 19
0
[PATCH 4/4] drm/nouveau: introduce CPU cache flushing macro
...ush_dcache_area(va, size); \
+ outer_flush_range(pa, pa + size); \
+} while (0)
+
+#else
+
+#define nv_cpu_cache_flush_area(va, size) \
+do { \
+} while (0)
+
+#endif /* defined(__arm__) */
+
#endif
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
index 0886f47e5244..b9c9729c5733 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -437,8 +437,10 @@ nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
mem = &mem[index];
if (is_iomem)
iowrite16_native(val, (void __force __iomem *)mem);
- else
+...
2014 May 19
0
[PATCH 3/4] drm/nouveau: hook up cache sync functions
...+++++++++++++++++++++
drivers/gpu/drm/nouveau/nouveau_bo.h | 20 ++++++++++++++++++++
drivers/gpu/drm/nouveau/nouveau_gem.c | 8 +++++++-
3 files changed, 59 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
index b6dc85c614be..0886f47e5244 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -407,6 +407,8 @@ nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
{
int ret;
+ nouveau_bo_sync_for_device(nvbo);
+
ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement,...
2014 May 19
0
[PATCH 4/4] drm/nouveau: introduce CPU cache flushing macro
...__cpuc_flush_dcache_area(va, size); \
> > + outer_flush_range(pa, pa + size); \
> > +} while (0)
>
> Couldn't this be a static inline function?
>
> > diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
> [...]
> > index 0886f47e5244..b9c9729c5733 100644
> > --- a/drivers/gpu/drm/nouveau/nouveau_bo.c
> > +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
> > @@ -437,8 +437,10 @@ nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
> > mem = &mem[index];
> > if (is_iomem)
> > i...
2014 Jun 12
0
[PATCH 4/4] drm/nouveau: introduce CPU cache flushing macro
...sh_range(pa, pa + size); \
>>> > +} while (0)
>>>
>>> Couldn't this be a static inline function?
>>>
>>> > diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
>>> [...]
>>> > index 0886f47e5244..b9c9729c5733 100644
>>> > --- a/drivers/gpu/drm/nouveau/nouveau_bo.c
>>> > +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
>>> > @@ -437,8 +437,10 @@ nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
>>> > mem = &mem[index];
>&g...