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...1805.00907.pdf). LLVM 5.0.2-final has [been tagged](http://lists.llvm.org/pipermail/llvm-dev/2018-May/122956.html). ## On the mailing lists * Richard Sandiford has posted an RFC on [adding variable-length register-sized vector types to C and C++](http://lists.llvm.org/pipermail/cfe-dev/2018-May/057830.html). Arm's Scalable Vector Extension is the motivating use case. * Rafael Avila de Espindola has announced that he is [leaving the LLLVM project](http://lists.llvm.org/pipermail/llvm-dev/2018-May/122922.html), citing unhappiness with changes in the community: specifically the adoption of a c...

...it > may not be possible to get a good answer. > > It's worth noting that we don't expect the last case (mixed scaled and > unscaled sizes) to occur. Richard Sandiford's proposed C extensions > (http://lists.llvm.org/pipermail/cfe-dev/2018-May/057830.html) explicitly > prohibits mixing fixed-size types into sizeless struct. > > I don't know if we need a 'maybe' or 'unknown' result for cases comparing scaled > vs. unscaled; I believe the gcc implementation of SVE allows for such > results, but that supports a...

...le to get a good > answer. > > > > It's worth noting that we don't expect the last case (mixed > scaled and > > unscaled sizes) to occur. Richard Sandiford's proposed C extensions > > (http://lists.llvm.org/pipermail/cfe-dev/2018-May/057830.html) > explicitly > > prohibits mixing fixed-size types into sizeless struct. > > > > I don't know if we need a 'maybe' or 'unknown' result for cases > comparing scaled > > vs. unscaled; I believe the gcc implementation of S...

...t > may not be possible to get a good answer. > > It's worth noting that we don't expect the last case (mixed scaled and > unscaled sizes) to occur. Richard Sandiford's proposed C extensions > (http://lists.llvm.org/pipermail/cfe-dev/2018-May/057830.html) explicitly > prohibits mixing fixed-size types into sizeless struct. > > I don't know if we need a 'maybe' or 'unknown' result for cases comparing scaled > vs. unscaled; I believe the gcc implementation of SVE allows for such > results, but that supports a g...

Hi, Now that Sander has committed enough MC support for SVE, here's an updated RFC for variable length vector support with a set of 14 patches (listed at the end) to demonstrate code generation for SVE using the extensions proposed in the RFC. I have some ideas about how to support RISC-V's upcoming extension alongside SVE; I'll send an email with some additional comments on