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This patchset centralizes the firmware-loading procedure to one set of functions instead of having each engine load its firmware as it pleases. This helps ensure that all firmware comes from the same place, namely nvidia/<chip>/. This changes where the firmware is fetched from for falcon/xtensa/bios, but these locations never seemed to have been official anyway. Also for most (all?) chips

...ce, 0x404490); - nvkm_error(subdev, "MACRO %08x\n", stat); + u32 pc = nvkm_rd32(device, 0x404494); + u32 op = nvkm_rd32(device, 0x40449c); + + nvkm_snprintbf(error, sizeof(error), gf100_macro_error, + stat & 0x1fffffff); + nvkm_error(subdev, "MACRO %08x [%s], pc: 0x%03x%s, op: 0x%08x\n", + stat, error, pc & 0x7ff, + (pc & 0x10000000) ? "" : " (invalid)", + op); + nvkm_wr32(device, 0x404490, 0xc0000000); nvkm_wr32(device, 0x400108, 0x00000080); trap &= ~0x00000080; } if (trap & 0x00000100) { -...

...ce, 0x404490); - nvkm_error(subdev, "MACRO %08x\n", stat); + u32 pc = nvkm_rd32(device, 0x404494); + u32 op = nvkm_rd32(device, 0x40449c); + + nvkm_snprintbf(error, sizeof(error), gf100_macro_error, + stat & 0x1fffffff); + nvkm_error(subdev, "MACRO %08x [%s], pc: 0x%03x%s, op: 0x%08x\n", + stat, error, pc & 0x7ff, + (pc & 0x10000000) ? "" : " (invalid)", + op); + nvkm_wr32(device, 0x404490, 0xc0000000); nvkm_wr32(device, 0x400108, 0x00000080); trap &= ~0x00000080; @@ -1088,10 +1149,9 @@ gf100_gr_trap_int...

...tical. + */ +{ + extern const char vsyscall_orig_start, vsyscall_orig_end; + int *l1 =3D (int *)page, *l2 =3D (int *)&vsyscall_orig_start; + int foo =3D vsyscall_orig_end - vsyscall_orig_start / 4; + for (i =3D 0; i < foo; i++) { + if (l1[i] !=3D l2[i]) { + printk("vsyscall - delta [%03x] orig %08x new %08x\n", + i, l2[i], l1[i]); + } + } +} +#endif +} +#else /* !CONFIG_COMPAT_VDSO */ +static inline void fixup_vsyscall_elf(char *page) {} +#endif /* CONFIG_COMPAT_VDSO */ + int __init sysenter_setup(void) { void *syscall_page =3D (void *)get_zeroed_page(GFP_ATOMIC); @@ -...

...tical. + */ +{ + extern const char vsyscall_orig_start, vsyscall_orig_end; + int *l1 =3D (int *)page, *l2 =3D (int *)&vsyscall_orig_start; + int foo =3D vsyscall_orig_end - vsyscall_orig_start / 4; + for (i =3D 0; i < foo; i++) { + if (l1[i] !=3D l2[i]) { + printk("vsyscall - delta [%03x] orig %08x new %08x\n", + i, l2[i], l1[i]); + } + } +} +#endif +} +#else /* !CONFIG_COMPAT_VDSO */ +static inline void fixup_vsyscall_elf(char *page) {} +#endif /* CONFIG_COMPAT_VDSO */ + int __init sysenter_setup(void) { void *syscall_page =3D (void *)get_zeroed_page(GFP_ATOMIC); @@ -...

...- *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2); - *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2); - spin_unlock_irqrestore(&ioapic_lock, flags); + entry = ioapic_read_entry(apic, i, 0); printk(KERN_DEBUG " %02x %03X %02X ", i, @@ -1212,7 +1225,6 @@ static void __init enable_IO_APIC(void) { int i8259_apic, i8259_pin; int i, apic; - unsigned long flags; /* Initialise dynamic irq_2_pin free list. */ irq_2_pin = xmalloc_array(struct irq_pin_list, PIN_MAP_SIZE); @...

...- *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2); - *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2); - spin_unlock_irqrestore(&ioapic_lock, flags); + entry = ioapic_read_entry(apic, i, 0); printk(KERN_DEBUG " %02x %03X %02X ", i, @@ -1212,7 +1225,6 @@ static void __init enable_IO_APIC(void) { int i8259_apic, i8259_pin; int i, apic; - unsigned long flags; /* Initialise dynamic irq_2_pin free list. */ irq_2_pin = xmalloc_array(struct irq_pin_list, PIN_MAP_SIZE); @...

...nouveau/core/engine/falcon.c index 5e077e4ed7f6..2914646c8709 100644 --- a/drivers/gpu/drm/nouveau/core/engine/falcon.c +++ b/drivers/gpu/drm/nouveau/core/engine/falcon.c @@ -119,7 +119,7 @@ _nouveau_falcon_init(struct nouveau_object *object) snprintf(name, sizeof(name), "nouveau/nv%02x_fuc%03x", device->chipset, falcon->addr >> 12); - ret = request_firmware(&fw, name, &device->pdev->dev); + ret = request_firmware(&fw, name, nv_device_base(device)); if (ret == 0) { falcon->code.data = vmemdup(fw->data, fw->size); falcon->c...

On 12/02/14 05:38, Alexandre Courbot wrote: > Upcoming mobile Kepler GPUs (such as GK20A) use the platform bus instead > of PCI to which Nouveau is tightly dependent. This patch allows Nouveau > to handle platform devices by: > > - abstracting PCI-dependent functions that were typically used for > resource querying and page mapping, > - introducing a nv_device_is_pci()

...+ len -= olen; + optend = p + olen; + switch (code) { + case CI_BRIDGE_IDENTIFICATION: + if (olen == CILEN_BRIDGELINEID) { + p += 2; + GETSHORT(cishort, p); + printer(arg, "Bridge-ID LAN=0x%03x Bridge=0x%X", + (cishort & 0xFFF0) >> 4, + cishort & 0x000F); + } + break; + + case CI_LINE_IDENTIFICATION: + if (olen == CILEN_BRIDGELINEID) { + p +=...

On Mon, Feb 10, 2014 at 8:50 PM, Thierry Reding <thierry.reding at gmail.com> wrote: > On Mon, Feb 10, 2014 at 02:53:00PM +0900, Alexandre Courbot wrote: > [...] >> diff --git a/drivers/gpu/drm/nouveau/core/engine/device/base.c b/drivers/gpu/drm/nouveau/core/engine/device/base.c > [...] >> +resource_size_t >> +nv_device_resource_start(struct nouveau_device *device,

...nouveau/core/engine/falcon.c index 5e077e4ed7f6..2914646c8709 100644 --- a/drivers/gpu/drm/nouveau/core/engine/falcon.c +++ b/drivers/gpu/drm/nouveau/core/engine/falcon.c @@ -119,7 +119,7 @@ _nouveau_falcon_init(struct nouveau_object *object) snprintf(name, sizeof(name), "nouveau/nv%02x_fuc%03x", device->chipset, falcon->addr >> 12); - ret = request_firmware(&fw, name, &device->pdev->dev); + ret = request_firmware(&fw, name, nv_device_base(device)); if (ret == 0) { falcon->code.data = vmemdup(fw->data, fw->size); falcon->c...

...++) { - struct IO_APIC_route_entry entry; - - spin_lock_irqsave(&ioapic_lock, flags); - *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2); - *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2); - spin_unlock_irqrestore(&ioapic_lock, flags); - - printk(KERN_DEBUG " %02x %03X %02X ", - i, - entry.dest.logical.logical_dest, - entry.dest.physical.physical_dest - ); - - printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", - entry.mask, - entry.trigger, - entry.irr, - entry.polarity, - entry.delivery_status, - entry.dest_mode,...

...++) { - struct IO_APIC_route_entry entry; - - spin_lock_irqsave(&ioapic_lock, flags); - *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2); - *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2); - spin_unlock_irqrestore(&ioapic_lock, flags); - - printk(KERN_DEBUG " %02x %03X %02X ", - i, - entry.dest.logical.logical_dest, - entry.dest.physical.physical_dest - ); - - printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", - entry.mask, - entry.trigger, - entry.irr, - entry.polarity, - entry.delivery_status, - entry.dest_mode,...

Dear Sir, I was trying to install bridge as we are installing scps gateway in our testbed.This requires us to install the bridge. Our Linux version is 2.4.18 ~3 and we are using redhat 7.2 Please let me know which is the bridge I should install and how to configure it. Before configuring the bridge what I should check in my configuration. Thanks for your time, Sincerely Rama ===== I hear

These chipsets include the VP2 engine which is composed of a bitstream processor (BSP) that decodes H.264 and a video processor (VP) which can do iDCT/mo-comp/etc for MPEG1/2, H.264, and VC-1. Both of these are driven by separate xtensa chips embedded in the hardware. This patch provides the mechanism to load the kernel for the xtensa chips and provide the necessary interactions to do the rest of

...lpfc_debugfs.c index c9a327b13e5c..325081ac6553 100644 --- a/drivers/scsi/lpfc/lpfc_debugfs.c +++ b/drivers/scsi/lpfc/lpfc_debugfs.c @@ -3339,11 +3339,10 @@ lpfc_idiag_pcicfg_read(struct file *file, char __user *buf, size_t nbytes, len += scnprintf(pbuffer+len, LPFC_PCI_CFG_SIZE-len, "%03x: %08x\n", where, u32val); break; case LPFC_PCI_CFG_BROWSE: /* browse all */ goto pcicfg_browse; - break; default: /* illegal count */ len = 0; break; } @@ -4379,11 +4378,11 @@ lpfc_idiag_queacc_write(struct file *file, const char __user *buf, goto pass_check; }...

...lpfc_debugfs.c index c9a327b13e5c..325081ac6553 100644 --- a/drivers/scsi/lpfc/lpfc_debugfs.c +++ b/drivers/scsi/lpfc/lpfc_debugfs.c @@ -3339,11 +3339,10 @@ lpfc_idiag_pcicfg_read(struct file *file, char __user *buf, size_t nbytes, len += scnprintf(pbuffer+len, LPFC_PCI_CFG_SIZE-len, "%03x: %08x\n", where, u32val); break; case LPFC_PCI_CFG_BROWSE: /* browse all */ goto pcicfg_browse; - break; default: /* illegal count */ len = 0; break; } @@ -4379,11 +4378,11 @@ lpfc_idiag_queacc_write(struct file *file, const char __user *buf, goto pass_check; }...

This round implements all of the review comments from V2 and all patches are now acked. Unless there are any objections I intend to apply later this morning. Ian.