search for: 0340f988

This can be done by declaring a register class with these registers and only using that register class as an operand in the instructions where it is legal. You then set as sub registers what you want to represent as the hi and lo registers for those 64bit registers. So something like this: def lo_comp : SubRegIndex; def hi_comp : SubRegIndex; def R1 : Register<1>; def R2 :

On Mips 32 there is traditionally a 64 bit HI/LO register for the result of multiplying two 64 bit numbers. There are corresponding instructions to load the LO and HI parts into individual 32 registers. On Mips with the DSP ASE (an application specific extension), there are actual 4 such pairs of registers. Is there a way to have special purpose 64 bit registers without actually having to

...> LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev > -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120905/0340f988/attachment.html>