Displaying 5 results from an estimated 5 matches for "01b80022".
Did you mean:
01b80026
2007 Jul 20
5
[LLVMdev] Seg faulting on vector ops
...00000000`01b80019 0f284c2404 movaps xmm1,xmmword ptr [esp+4] <--
this seg faults because esp+4 isn't 16-byte aligned
What is that line trying to achieve? X is at [esp+24]. There weren't
any other parameters.
00000000`01b8001e f30f10c8 movss xmm1,xmm0
00000000`01b80022 8b442424 mov eax,dword ptr [esp+24h]
00000000`01b80026 660fc4c802 pinsrw xmm1,eax,2
00000000`01b8002b 89c1 mov ecx,eax
00000000`01b8002d c1e910 shr ecx,10h
00000000`01b80030 660fc4c903 pinsrw xmm1,ecx,3
00000000`01b80035 660fc4c804 pinsrw...
2007 Jul 21
0
[LLVMdev] Seg faulting on vector ops
...xmm1,xmmword ptr [esp+4] <--
> this seg faults because esp+4 isn't 16-byte aligned
>
> What is that line trying to achieve? X is at [esp+24]. There weren't
> any other parameters.
>
>
>
> 00000000`01b8001e f30f10c8 movss xmm1,xmm0
>
> 00000000`01b80022 8b442424 mov eax,dword ptr [esp+24h]
>
> 00000000`01b80026 660fc4c802 pinsrw xmm1,eax,2
>
> 00000000`01b8002b 89c1 mov ecx,eax
>
> 00000000`01b8002d c1e910 shr ecx,10h
>
> 00000000`01b80030 660fc4c903 pinsrw xmm1,ecx,3
>...
2007 Jul 24
2
[LLVMdev] Seg faulting on vector ops
...eg faults because esp+4 isn't 16-byte aligned
>>
>> What is that line trying to achieve? X is at [esp+24]. There
>> weren't
>> any other parameters.
>>
>>
>>
>> 00000000`01b8001e f30f10c8 movss xmm1,xmm0
>>
>> 00000000`01b80022 8b442424 mov eax,dword ptr [esp+24h]
>>
>> 00000000`01b80026 660fc4c802 pinsrw xmm1,eax,2
>>
>> 00000000`01b8002b 89c1 mov ecx,eax
>>
>> 00000000`01b8002d c1e910 shr ecx,10h
>>
>> 00000000`01b80030 660fc4c9...
2007 Jul 20
0
[LLVMdev] Seg faulting on vector ops
...movaps xmm1,xmmword ptr [esp
> +4] ß this seg faults because esp+4 isn’t 16-byte aligned
>
> What is that line trying to achieve? X is at [esp+24]. There
> weren’t any other parameters.
>
>
>
> 00000000`01b8001e f30f10c8 movss xmm1,xmm0
>
> 00000000`01b80022 8b442424 mov eax,dword ptr [esp+24h]
>
> 00000000`01b80026 660fc4c802 pinsrw xmm1,eax,2
>
> 00000000`01b8002b 89c1 mov ecx,eax
>
> 00000000`01b8002d c1e910 shr ecx,10h
>
> 00000000`01b80030 660fc4c903 pinsrw xmm1,ecx,3
>...
2007 Jul 26
0
[LLVMdev] Seg faulting on vector ops
...yte aligned
>>>
>>> What is that line trying to achieve? X is at [esp+24]. There
>>> weren't
>>> any other parameters.
>>>
>>>
>>>
>>> 00000000`01b8001e f30f10c8 movss xmm1,xmm0
>>>
>>> 00000000`01b80022 8b442424 mov eax,dword ptr [esp+24h]
>>>
>>> 00000000`01b80026 660fc4c802 pinsrw xmm1,eax,2
>>>
>>> 00000000`01b8002b 89c1 mov ecx,eax
>>>
>>> 00000000`01b8002d c1e910 shr ecx,10h
>>>
>>...