search for: 01b80019

Displaying 5 results from an estimated 5 matches for "01b80019".

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2007 Jul 20
5
[LLVMdev] Seg faulting on vector ops
...4, i32 3 ; <float> [#uses =1] ret float %s } In Intel assembly, I get the following: 00000000`01b80010 83ec20 sub esp,20h 00000000`01b80013 f30f10442424 movss xmm0,dword ptr [esp+24h] <-- this loads x into the low float of xmm0 00000000`01b80019 0f284c2404 movaps xmm1,xmmword ptr [esp+4] <-- this seg faults because esp+4 isn't 16-byte aligned What is that line trying to achieve? X is at [esp+24]. There weren't any other parameters. 00000000`01b8001e f30f10c8 movss xmm1,xmm0 00000000`01b80022 8b442424...
2007 Jul 21
0
[LLVMdev] Seg faulting on vector ops
...loat %s > > } > > > > In Intel assembly, I get the following: > > > > 00000000`01b80010 83ec20 sub esp,20h > > 00000000`01b80013 f30f10442424 movss xmm0,dword ptr [esp+24h] <-- > this loads x into the low float of xmm0 > > 00000000`01b80019 0f284c2404 movaps xmm1,xmmword ptr [esp+4] <-- > this seg faults because esp+4 isn't 16-byte aligned > > What is that line trying to achieve? X is at [esp+24]. There weren't > any other parameters. > > > > 00000000`01b8001e f30f10c8 movss xmm1,x...
2007 Jul 24
2
[LLVMdev] Seg faulting on vector ops
...l assembly, I get the following: >> >> >> >> 00000000`01b80010 83ec20 sub esp,20h >> >> 00000000`01b80013 f30f10442424 movss xmm0,dword ptr [esp >> +24h] <-- >> this loads x into the low float of xmm0 >> >> 00000000`01b80019 0f284c2404 movaps xmm1,xmmword ptr [esp >> +4] <-- >> this seg faults because esp+4 isn't 16-byte aligned >> >> What is that line trying to achieve? X is at [esp+24]. There >> weren't >> any other parameters. >> >> >> &gt...
2007 Jul 20
0
[LLVMdev] Seg faulting on vector ops
...t float %s > > } > > > > In Intel assembly, I get the following: > > > > 00000000`01b80010 83ec20 sub esp,20h > > 00000000`01b80013 f30f10442424 movss xmm0,dword ptr [esp > +24h] ß this loads x into the low float of xmm0 > > 00000000`01b80019 0f284c2404 movaps xmm1,xmmword ptr [esp > +4] ß this seg faults because esp+4 isn’t 16-byte aligned > > What is that line trying to achieve? X is at [esp+24]. There > weren’t any other parameters. > > > > 00000000`01b8001e f30f10c8 movss xmm1,xmm0 >...
2007 Jul 26
0
[LLVMdev] Seg faulting on vector ops
...t;> >>> >>> >>> 00000000`01b80010 83ec20 sub esp,20h >>> >>> 00000000`01b80013 f30f10442424 movss xmm0,dword ptr [esp >>> +24h] <-- >>> this loads x into the low float of xmm0 >>> >>> 00000000`01b80019 0f284c2404 movaps xmm1,xmmword ptr [esp >>> +4] <-- >>> this seg faults because esp+4 isn't 16-byte aligned >>> >>> What is that line trying to achieve? X is at [esp+24]. There >>> weren't >>> any other parameters. >>&...