Displaying 5 results from an estimated 5 matches for "01b80013".
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01b80010
2007 Jul 20
5
[LLVMdev] Seg faulting on vector ops
...oat> %v3, float %x, i32 3
; <<4 x
float>> [#uses=1]
%s = extractelement <4 x float> %v4, i32 3 ;
<float> [#uses
=1]
ret float %s
}
In Intel assembly, I get the following:
00000000`01b80010 83ec20 sub esp,20h
00000000`01b80013 f30f10442424 movss xmm0,dword ptr [esp+24h] <--
this loads x into the low float of xmm0
00000000`01b80019 0f284c2404 movaps xmm1,xmmword ptr [esp+4] <--
this seg faults because esp+4 isn't 16-byte aligned
What is that line trying to achieve? X is at [esp+24]. There were...
2007 Jul 21
0
[LLVMdev] Seg faulting on vector ops
...%s = extractelement <4 x float> %v4, i32 3 ;
> <float> [#uses
>
> =1]
>
> ret float %s
>
> }
>
>
>
> In Intel assembly, I get the following:
>
>
>
> 00000000`01b80010 83ec20 sub esp,20h
>
> 00000000`01b80013 f30f10442424 movss xmm0,dword ptr [esp+24h] <--
> this loads x into the low float of xmm0
>
> 00000000`01b80019 0f284c2404 movaps xmm1,xmmword ptr [esp+4] <--
> this seg faults because esp+4 isn't 16-byte aligned
>
> What is that line trying to achieve? X...
2007 Jul 24
2
[LLVMdev] Seg faulting on vector ops
...>> <float> [#uses
>>
>> =1]
>>
>> ret float %s
>>
>> }
>>
>>
>>
>> In Intel assembly, I get the following:
>>
>>
>>
>> 00000000`01b80010 83ec20 sub esp,20h
>>
>> 00000000`01b80013 f30f10442424 movss xmm0,dword ptr [esp
>> +24h] <--
>> this loads x into the low float of xmm0
>>
>> 00000000`01b80019 0f284c2404 movaps xmm1,xmmword ptr [esp
>> +4] <--
>> this seg faults because esp+4 isn't 16-byte aligned
>>
&g...
2007 Jul 20
0
[LLVMdev] Seg faulting on vector ops
...%s = extractelement <4 x float> %v4, i32 3 ;
> <float> [#uses
>
> =1]
>
> ret float %s
>
> }
>
>
>
> In Intel assembly, I get the following:
>
>
>
> 00000000`01b80010 83ec20 sub esp,20h
>
> 00000000`01b80013 f30f10442424 movss xmm0,dword ptr [esp
> +24h] ß this loads x into the low float of xmm0
>
> 00000000`01b80019 0f284c2404 movaps xmm1,xmmword ptr [esp
> +4] ß this seg faults because esp+4 isn’t 16-byte aligned
>
> What is that line trying to achieve? X is at [es...
2007 Jul 26
0
[LLVMdev] Seg faulting on vector ops
...;>>
>>> ret float %s
>>>
>>> }
>>>
>>>
>>>
>>> In Intel assembly, I get the following:
>>>
>>>
>>>
>>> 00000000`01b80010 83ec20 sub esp,20h
>>>
>>> 00000000`01b80013 f30f10442424 movss xmm0,dword ptr [esp
>>> +24h] <--
>>> this loads x into the low float of xmm0
>>>
>>> 00000000`01b80019 0f284c2404 movaps xmm1,xmmword ptr [esp
>>> +4] <--
>>> this seg faults because esp+4 isn't 16-by...