Displaying 3 results from an estimated 3 matches for "0182b7e0".
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018270
2008 Oct 23
1
[LLVMdev] Register class conversions
...hat can convert between the 64bit and 32 bit and back. So, if
this situation is detected, can I specify for llvm to insert some sort
of conversion instead of just aborting with:
Register class of operand and regclass of use don't agree!
Operand = 2
Op->Val = 01828560: f64,ch = PTRLOAD_f64 0182B7E0, 0182B4B0, 0182B868,
01828450
MI = %reg1028<def> = CMP_32 41, %reg1027
VReg = 1027
VReg RegClass size = 8, align = 8
Expected RegClass size = 4, align = 4
Fatal error, aborting.
Both of these patterns are matched via tablegen, so I'm not sure how it
is coming to this conclusi...
2008 Oct 23
0
[LLVMdev] Register class conversions
On Oct 22, 2008, at 1:28 PM, Villmow, Micah wrote:
> Is there a simple way to specify the relationship between two
> different register classes of various sizes and alignments as being
> legal to convert between them?
I don't get it. What does it mean to "convert" between two register
classes? You can move between different register classes.
> I have my backend
2008 Oct 22
2
[LLVMdev] Register class conversions
Is there a simple way to specify the relationship between two different
register classes of various sizes and alignments as being legal to
convert between them?
I have my backend written up using a single register class for i32, i64,
f32 and f64 types, however, because the type information is not
propagated down to the machine instruction register level, it is not
known to me how to determine