search for: 010llx

...debug(subdev, "FBP %d: disabled\n", fbp); 596 } 597 } 598 599 lower = lcomm * ltcn; 600 ubase = lcomm + func->upper; 601 usize = total - lower; 602 603 nvkm_debug(subdev, "Lower: %4lld MiB @ %010llx\n", lower >> 20, 0ULL); 604 nvkm_debug(subdev, "Upper: %4lld MiB @ %010llx\n", usize >> 20, ubase); 605 nvkm_debug(subdev, "Total: %4lld MiB\n", total >> 20); 606 607 ret = nvkm_ram_ctor(func, fb, type, total, 0, ra...

...t; nvkm_error(subdev, > - "fault %02x [%s] at %016llx engine %02x [%s] client %02x " > + "fault %02x [%s] at %016llx aperture %02x engine %02x [%s] client %02x " > "[%s%s] reason %02x [%s] on channel %d [%010llx %s]\n", > info->access, ea ? ea->name : "", info->addr, > + info->aperture, > info->engine, ee ? ee->name : en, > info->client, ct, ec ? ec->name : "", >...

..."unk"; + if (engctx) { + struct nouveau_client *client = nouveau_client(engctx); + if (client) + client_name = client->name; + } nv_error(priv, ""); nouveau_bitfield_print(nv50_graph_intr_name, show); printk("\n"); - nv_error(priv, "ch %d [0x%010llx] subc %d class 0x%04x " - "mthd 0x%04x data 0x%08x\n", - chid, (u64)inst << 12, subc, class, mthd, data); + nv_error(priv, + "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", + chid, (u64)inst << 12, client_name, subc, cla...

...km_fifo_chan_inst_locked(&fifo->base, info->inst); nvkm_error(subdev, - "fault %02x [%s] at %016llx engine %02x [%s] client %02x " + "fault %02x [%s] at %016llx aperture %02x engine %02x [%s] client %02x " "[%s%s] reason %02x [%s] on channel %d [%010llx %s]\n", info->access, ea ? ea->name : "", info->addr, + info->aperture, info->engine, ee ? ee->name : en, info->client, ct, ec ? ec->name : "", info->reason, er ? er->name : "", chan ? chan->chid : -1, d...

--- drivers/gpu/drm/nouveau/core/include/subdev/ltcg.h | 7 + drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.c | 55 +++++---- drivers/gpu/drm/nouveau/core/subdev/ltcg/nvc0.c | 129 +++++++++++++++++++- drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c | 58 +++++++++- 4 files changed, 220 insertions(+), 29 deletions(-) diff --git

From: Thierry Reding <treding at nvidia.com> Hi Ben, these are a couple of patches that are in preparation for adding GV11B support. The fundamental issue that these are trying to solve is that the GV11B is the first Tegra incarnation of the GPU where the aperture really matters. All prior generations would accept any of them. For dGPUs we usually allocate memory in VRAM, so the default

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- I made the assumption that showing the address is generally useful. Worst case, it won't make sense but still be displayed. Seems simpler than special-casing things. drivers/gpu/drm/nouveau/core/engine/graph/nv50.c | 117 ++++++++++++----------- 1 file changed, 63 insertions(+), 54 deletions(-) diff --git

Hi there, Resending these now that they've had some more polish and testing, and I heard that Ben's vacation is over :-) These patches work as a starting point for more explicit error mechanisms and better robustness. At the moment, when a job hangs or faults, it seems that nouveau doesn't quite know how to handle the situation and often results in a hang. Some of these situations

This is an initial series of patches to improve channel recovery on Turing GPUs with the goal of improving reliability enough to eventually enable SVM for Turing. It's likely follow up patches will be required to fully address problems with less trivial workloads than what I have been able to test thus far. This series primarily addresses a number of hardware changes to interrupt layout and